Data Structures
union	MSR_IA32_PLATFORM_ID_REGISTER

union	MSR_IA32_APIC_BASE_REGISTER

union	MSR_IA32_FEATURE_CONTROL_REGISTER

union	MSR_IA32_BIOS_SIGN_ID_REGISTER

union	MSR_IA32_SMM_MONITOR_CTL_REGISTER

struct	MSEG_HEADER

union	MSR_IA32_MTRRCAP_REGISTER

union	MSR_IA32_SYSENTER_CS_REGISTER

union	MSR_IA32_MCG_CAP_REGISTER

union	MSR_IA32_MCG_STATUS_REGISTER

union	MSR_IA32_PERFEVTSEL_REGISTER

union	MSR_IA32_PERF_STATUS_REGISTER

union	MSR_IA32_PERF_CTL_REGISTER

union	MSR_IA32_CLOCK_MODULATION_REGISTER

union	MSR_IA32_THERM_INTERRUPT_REGISTER

union	MSR_IA32_THERM_STATUS_REGISTER

union	MSR_IA32_MISC_ENABLE_REGISTER

union	MSR_IA32_ENERGY_PERF_BIAS_REGISTER

union	MSR_IA32_PACKAGE_THERM_STATUS_REGISTER

union	MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER

union	MSR_IA32_DEBUGCTL_REGISTER

union	MSR_IA32_SMRR_PHYSBASE_REGISTER

union	MSR_IA32_SMRR_PHYSMASK_REGISTER

union	MSR_IA32_DCA_0_CAP_REGISTER

union	MSR_IA32_MTRR_PHYSBASE_REGISTER

union	MSR_IA32_MTRR_PHYSMASK_REGISTER

union	MSR_IA32_PAT_REGISTER

union	MSR_IA32_MC_CTL2_REGISTER

union	MSR_IA32_MTRR_DEF_TYPE_REGISTER

union	MSR_IA32_PERF_CAPABILITIES_REGISTER

union	MSR_IA32_FIXED_CTR_CTRL_REGISTER

union	MSR_IA32_PERF_GLOBAL_STATUS_REGISTER

union	MSR_IA32_PERF_GLOBAL_CTRL_REGISTER

union	MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER

union	MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER

union	MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER

union	MSR_IA32_PERF_GLOBAL_INUSE_REGISTER

union	MSR_IA32_PEBS_ENABLE_REGISTER

union	MSR_IA32_VMX_BASIC_REGISTER

union	IA32_VMX_MISC_REGISTER

union	MSR_IA32_MCG_EXT_CTL_REGISTER

union	MSR_IA32_SGX_SVN_STATUS_REGISTER

union	MSR_IA32_RTIT_OUTPUT_BASE_REGISTER

union	MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER

union	RTIT_TOPA_TABLE_ENTRY

union	MSR_IA32_RTIT_CTL_REGISTER

union	MSR_IA32_RTIT_STATUS_REGISTER

union	MSR_IA32_RTIT_CR3_MATCH_REGISTER

union	MSR_IA32_RTIT_ADDR_REGISTER

union	MSR_IA32_PM_ENABLE_REGISTER

union	MSR_IA32_HWP_CAPABILITIES_REGISTER

union	MSR_IA32_HWP_REQUEST_PKG_REGISTER

union	MSR_IA32_HWP_INTERRUPT_REGISTER

union	MSR_IA32_HWP_REQUEST_REGISTER

union	MSR_IA32_HWP_STATUS_REGISTER

union	MSR_IA32_DEBUG_INTERFACE_REGISTER

union	MSR_IA32_L3_QOS_CFG_REGISTER

union	MSR_IA32_L2_QOS_CFG_REGISTER

union	MSR_IA32_QM_EVTSEL_REGISTER

union	MSR_IA32_QM_CTR_REGISTER

union	MSR_IA32_PQR_ASSOC_REGISTER

union	MSR_IA32_BNDCFGS_REGISTER

union	MSR_IA32_XSS_REGISTER

union	MSR_IA32_PKG_HDC_CTL_REGISTER

union	MSR_IA32_PM_CTL1_REGISTER

union	MSR_IA32_EFER_REGISTER

union	MSR_IA32_TSC_AUX_REGISTER

Macros
#define	MSR_IA32_P5_MC_ADDR 0x00000000

#define	MSR_IA32_P5_MC_TYPE 0x00000001

#define	MSR_IA32_MONITOR_FILTER_SIZE 0x00000006

#define	MSR_IA32_TIME_STAMP_COUNTER 0x00000010

#define	MSR_IA32_PLATFORM_ID 0x00000017

#define	MSR_IA32_APIC_BASE 0x0000001B

#define	MSR_IA32_FEATURE_CONTROL 0x0000003A

#define	MSR_IA32_TSC_ADJUST 0x0000003B

#define	MSR_IA32_BIOS_UPDT_TRIG 0x00000079

#define	MSR_IA32_BIOS_SIGN_ID 0x0000008B

#define	MSR_IA32_SMM_MONITOR_CTL 0x0000009B

#define	MSR_IA32_SMBASE 0x0000009E

#define	MSR_IA32_MPERF 0x000000E7

#define	MSR_IA32_APERF 0x000000E8

#define	MSR_IA32_MTRRCAP 0x000000FE

#define	MSR_IA32_SYSENTER_CS 0x00000174

#define	MSR_IA32_SYSENTER_ESP 0x00000175

#define	MSR_IA32_SYSENTER_EIP 0x00000176

#define	MSR_IA32_MCG_CAP 0x00000179

#define	MSR_IA32_MCG_STATUS 0x0000017A

#define	MSR_IA32_MCG_CTL 0x0000017B

#define	MSR_IA32_PERF_STATUS 0x00000198

#define	MSR_IA32_PERF_CTL 0x00000199

#define	MSR_IA32_CLOCK_MODULATION 0x0000019A

#define	MSR_IA32_THERM_INTERRUPT 0x0000019B

#define	MSR_IA32_THERM_STATUS 0x0000019C

#define	MSR_IA32_MISC_ENABLE 0x000001A0

#define	MSR_IA32_ENERGY_PERF_BIAS 0x000001B0

#define	MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1

#define	MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2

#define	MSR_IA32_DEBUGCTL 0x000001D9

#define	MSR_IA32_SMRR_PHYSBASE 0x000001F2

#define	MSR_IA32_SMRR_PHYSMASK 0x000001F3

#define	MSR_IA32_PLATFORM_DCA_CAP 0x000001F8

#define	MSR_IA32_CPU_DCA_CAP 0x000001F9

#define	MSR_IA32_DCA_0_CAP 0x000001FA

#define	MSR_IA32_MTRR_FIX64K_00000 0x00000250

#define	MSR_IA32_MTRR_FIX16K_80000 0x00000258

#define	MSR_IA32_MTRR_FIX16K_A0000 0x00000259

#define	MSR_IA32_MTRR_FIX4K_C0000 0x00000268

#define	MSR_IA32_MTRR_FIX4K_C8000 0x00000269

#define	MSR_IA32_MTRR_FIX4K_D0000 0x0000026A

#define	MSR_IA32_MTRR_FIX4K_D8000 0x0000026B

#define	MSR_IA32_MTRR_FIX4K_E0000 0x0000026C

#define	MSR_IA32_MTRR_FIX4K_E8000 0x0000026D

#define	MSR_IA32_MTRR_FIX4K_F0000 0x0000026E

#define	MSR_IA32_MTRR_FIX4K_F8000 0x0000026F

#define	MSR_IA32_PAT 0x00000277

#define	MSR_IA32_MTRR_DEF_TYPE 0x000002FF

#define	MSR_IA32_FIXED_CTR0 0x00000309

#define	MSR_IA32_FIXED_CTR1 0x0000030A

#define	MSR_IA32_FIXED_CTR2 0x0000030B

#define	MSR_IA32_PERF_CAPABILITIES 0x00000345

#define	MSR_IA32_FIXED_CTR_CTRL 0x0000038D

#define	MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E

#define	MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F

#define	MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390

#define	MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390

#define	MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391

#define	MSR_IA32_PERF_GLOBAL_INUSE 0x00000392

#define	MSR_IA32_PEBS_ENABLE 0x000003F1

#define	MSR_IA32_VMX_BASIC 0x00000480

#define	MSR_IA32_VMX_PINBASED_CTLS 0x00000481

#define	MSR_IA32_VMX_PROCBASED_CTLS 0x00000482

#define	MSR_IA32_VMX_EXIT_CTLS 0x00000483

#define	MSR_IA32_VMX_ENTRY_CTLS 0x00000484

#define	MSR_IA32_VMX_MISC 0x00000485

#define	MSR_IA32_VMX_CR0_FIXED0 0x00000486

#define	MSR_IA32_VMX_CR0_FIXED1 0x00000487

#define	MSR_IA32_VMX_CR4_FIXED0 0x00000488

#define	MSR_IA32_VMX_CR4_FIXED1 0x00000489

#define	MSR_IA32_VMX_VMCS_ENUM 0x0000048A

#define	MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B

#define	MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C

#define	MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D

#define	MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E

#define	MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F

#define	MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490

#define	MSR_IA32_VMX_VMFUNC 0x00000491

#define	MSR_IA32_MCG_EXT_CTL 0x000004D0

#define	MSR_IA32_SGX_SVN_STATUS 0x00000500

#define	MSR_IA32_RTIT_OUTPUT_BASE 0x00000560

#define	MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561

#define	MSR_IA32_RTIT_CTL 0x00000570

#define	MSR_IA32_RTIT_STATUS 0x00000571

#define	MSR_IA32_RTIT_CR3_MATCH 0x00000572

#define	MSR_IA32_DS_AREA 0x00000600

#define	MSR_IA32_TSC_DEADLINE 0x000006E0

#define	MSR_IA32_PM_ENABLE 0x00000770

#define	MSR_IA32_HWP_CAPABILITIES 0x00000771

#define	MSR_IA32_HWP_REQUEST_PKG 0x00000772

#define	MSR_IA32_HWP_INTERRUPT 0x00000773

#define	MSR_IA32_HWP_REQUEST 0x00000774

#define	MSR_IA32_HWP_STATUS 0x00000777

#define	MSR_IA32_X2APIC_APICID 0x00000802

#define	MSR_IA32_X2APIC_VERSION 0x00000803

#define	MSR_IA32_X2APIC_TPR 0x00000808

#define	MSR_IA32_X2APIC_PPR 0x0000080A

#define	MSR_IA32_X2APIC_EOI 0x0000080B

#define	MSR_IA32_X2APIC_LDR 0x0000080D

#define	MSR_IA32_X2APIC_SIVR 0x0000080F

#define	MSR_IA32_X2APIC_ESR 0x00000828

#define	MSR_IA32_X2APIC_LVT_CMCI 0x0000082F

#define	MSR_IA32_X2APIC_ICR 0x00000830

#define	MSR_IA32_X2APIC_LVT_TIMER 0x00000832

#define	MSR_IA32_X2APIC_LVT_THERMAL 0x00000833

#define	MSR_IA32_X2APIC_LVT_PMI 0x00000834

#define	MSR_IA32_X2APIC_LVT_LINT0 0x00000835

#define	MSR_IA32_X2APIC_LVT_LINT1 0x00000836

#define	MSR_IA32_X2APIC_LVT_ERROR 0x00000837

#define	MSR_IA32_X2APIC_INIT_COUNT 0x00000838

#define	MSR_IA32_X2APIC_CUR_COUNT 0x00000839

#define	MSR_IA32_X2APIC_DIV_CONF 0x0000083E

#define	MSR_IA32_X2APIC_SELF_IPI 0x0000083F

#define	MSR_IA32_DEBUG_INTERFACE 0x00000C80

#define	MSR_IA32_L3_QOS_CFG 0x00000C81

#define	MSR_IA32_L2_QOS_CFG 0x00000C82

#define	MSR_IA32_QM_EVTSEL 0x00000C8D

#define	MSR_IA32_QM_CTR 0x00000C8E

#define	MSR_IA32_PQR_ASSOC 0x00000C8F

#define	MSR_IA32_BNDCFGS 0x00000D90

#define	MSR_IA32_XSS 0x00000DA0

#define	MSR_IA32_PKG_HDC_CTL 0x00000DB0

#define	MSR_IA32_PM_CTL1 0x00000DB1

#define	MSR_IA32_THREAD_STALL 0x00000DB2

#define	MSR_IA32_EFER 0xC0000080

#define	MSR_IA32_STAR 0xC0000081

#define	MSR_IA32_LSTAR 0xC0000082

#define	MSR_IA32_CSTAR 0xC0000083

#define	MSR_IA32_FMASK 0xC0000084

#define	MSR_IA32_FS_BASE 0xC0000100

#define	MSR_IA32_GS_BASE 0xC0000101

#define	MSR_IA32_KERNEL_GS_BASE 0xC0000102

#define	MSR_IA32_TSC_AUX 0xC0000103


#define	MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C

#define	MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D

#define	MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E

#define	MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F


#define	STM_FEATURES_IA32E 0x1


#define	MSR_IA32_PMC0 0x000000C1

#define	MSR_IA32_PMC1 0x000000C2

#define	MSR_IA32_PMC2 0x000000C3

#define	MSR_IA32_PMC3 0x000000C4

#define	MSR_IA32_PMC4 0x000000C5

#define	MSR_IA32_PMC5 0x000000C6

#define	MSR_IA32_PMC6 0x000000C7

#define	MSR_IA32_PMC7 0x000000C8


#define	MSR_IA32_PERFEVTSEL0 0x00000186

#define	MSR_IA32_PERFEVTSEL1 0x00000187

#define	MSR_IA32_PERFEVTSEL2 0x00000188

#define	MSR_IA32_PERFEVTSEL3 0x00000189


#define	MSR_IA32_MTRR_PHYSBASE0 0x00000200

#define	MSR_IA32_MTRR_PHYSBASE1 0x00000202

#define	MSR_IA32_MTRR_PHYSBASE2 0x00000204

#define	MSR_IA32_MTRR_PHYSBASE3 0x00000206

#define	MSR_IA32_MTRR_PHYSBASE4 0x00000208

#define	MSR_IA32_MTRR_PHYSBASE5 0x0000020A

#define	MSR_IA32_MTRR_PHYSBASE6 0x0000020C

#define	MSR_IA32_MTRR_PHYSBASE7 0x0000020E

#define	MSR_IA32_MTRR_PHYSBASE8 0x00000210

#define	MSR_IA32_MTRR_PHYSBASE9 0x00000212


#define	MSR_IA32_MTRR_PHYSMASK0 0x00000201

#define	MSR_IA32_MTRR_PHYSMASK1 0x00000203

#define	MSR_IA32_MTRR_PHYSMASK2 0x00000205

#define	MSR_IA32_MTRR_PHYSMASK3 0x00000207

#define	MSR_IA32_MTRR_PHYSMASK4 0x00000209

#define	MSR_IA32_MTRR_PHYSMASK5 0x0000020B

#define	MSR_IA32_MTRR_PHYSMASK6 0x0000020D

#define	MSR_IA32_MTRR_PHYSMASK7 0x0000020F

#define	MSR_IA32_MTRR_PHYSMASK8 0x00000211

#define	MSR_IA32_MTRR_PHYSMASK9 0x00000213


#define	MSR_IA32_MC0_CTL2 0x00000280

#define	MSR_IA32_MC1_CTL2 0x00000281

#define	MSR_IA32_MC2_CTL2 0x00000282

#define	MSR_IA32_MC3_CTL2 0x00000283

#define	MSR_IA32_MC4_CTL2 0x00000284

#define	MSR_IA32_MC5_CTL2 0x00000285

#define	MSR_IA32_MC6_CTL2 0x00000286

#define	MSR_IA32_MC7_CTL2 0x00000287

#define	MSR_IA32_MC8_CTL2 0x00000288

#define	MSR_IA32_MC9_CTL2 0x00000289

#define	MSR_IA32_MC10_CTL2 0x0000028A

#define	MSR_IA32_MC11_CTL2 0x0000028B

#define	MSR_IA32_MC12_CTL2 0x0000028C

#define	MSR_IA32_MC13_CTL2 0x0000028D

#define	MSR_IA32_MC14_CTL2 0x0000028E

#define	MSR_IA32_MC15_CTL2 0x0000028F

#define	MSR_IA32_MC16_CTL2 0x00000290

#define	MSR_IA32_MC17_CTL2 0x00000291

#define	MSR_IA32_MC18_CTL2 0x00000292

#define	MSR_IA32_MC19_CTL2 0x00000293

#define	MSR_IA32_MC20_CTL2 0x00000294

#define	MSR_IA32_MC21_CTL2 0x00000295

#define	MSR_IA32_MC22_CTL2 0x00000296

#define	MSR_IA32_MC23_CTL2 0x00000297

#define	MSR_IA32_MC24_CTL2 0x00000298

#define	MSR_IA32_MC25_CTL2 0x00000299

#define	MSR_IA32_MC26_CTL2 0x0000029A

#define	MSR_IA32_MC27_CTL2 0x0000029B

#define	MSR_IA32_MC28_CTL2 0x0000029C

#define	MSR_IA32_MC29_CTL2 0x0000029D

#define	MSR_IA32_MC30_CTL2 0x0000029E

#define	MSR_IA32_MC31_CTL2 0x0000029F


#define	MSR_IA32_MC0_CTL 0x00000400

#define	MSR_IA32_MC1_CTL 0x00000404

#define	MSR_IA32_MC2_CTL 0x00000408

#define	MSR_IA32_MC3_CTL 0x0000040C

#define	MSR_IA32_MC4_CTL 0x00000410

#define	MSR_IA32_MC5_CTL 0x00000414

#define	MSR_IA32_MC6_CTL 0x00000418

#define	MSR_IA32_MC7_CTL 0x0000041C

#define	MSR_IA32_MC8_CTL 0x00000420

#define	MSR_IA32_MC9_CTL 0x00000424

#define	MSR_IA32_MC10_CTL 0x00000428

#define	MSR_IA32_MC11_CTL 0x0000042C

#define	MSR_IA32_MC12_CTL 0x00000430

#define	MSR_IA32_MC13_CTL 0x00000434

#define	MSR_IA32_MC14_CTL 0x00000438

#define	MSR_IA32_MC15_CTL 0x0000043C

#define	MSR_IA32_MC16_CTL 0x00000440

#define	MSR_IA32_MC17_CTL 0x00000444

#define	MSR_IA32_MC18_CTL 0x00000448

#define	MSR_IA32_MC19_CTL 0x0000044C

#define	MSR_IA32_MC20_CTL 0x00000450

#define	MSR_IA32_MC21_CTL 0x00000454

#define	MSR_IA32_MC22_CTL 0x00000458

#define	MSR_IA32_MC23_CTL 0x0000045C

#define	MSR_IA32_MC24_CTL 0x00000460

#define	MSR_IA32_MC25_CTL 0x00000464

#define	MSR_IA32_MC26_CTL 0x00000468

#define	MSR_IA32_MC27_CTL 0x0000046C

#define	MSR_IA32_MC28_CTL 0x00000470


#define	MSR_IA32_MC0_STATUS 0x00000401

#define	MSR_IA32_MC1_STATUS 0x00000405

#define	MSR_IA32_MC2_STATUS 0x00000409

#define	MSR_IA32_MC3_STATUS 0x0000040D

#define	MSR_IA32_MC4_STATUS 0x00000411

#define	MSR_IA32_MC5_STATUS 0x00000415

#define	MSR_IA32_MC6_STATUS 0x00000419

#define	MSR_IA32_MC7_STATUS 0x0000041D

#define	MSR_IA32_MC8_STATUS 0x00000421

#define	MSR_IA32_MC9_STATUS 0x00000425

#define	MSR_IA32_MC10_STATUS 0x00000429

#define	MSR_IA32_MC11_STATUS 0x0000042D

#define	MSR_IA32_MC12_STATUS 0x00000431

#define	MSR_IA32_MC13_STATUS 0x00000435

#define	MSR_IA32_MC14_STATUS 0x00000439

#define	MSR_IA32_MC15_STATUS 0x0000043D

#define	MSR_IA32_MC16_STATUS 0x00000441

#define	MSR_IA32_MC17_STATUS 0x00000445

#define	MSR_IA32_MC18_STATUS 0x00000449

#define	MSR_IA32_MC19_STATUS 0x0000044D

#define	MSR_IA32_MC20_STATUS 0x00000451

#define	MSR_IA32_MC21_STATUS 0x00000455

#define	MSR_IA32_MC22_STATUS 0x00000459

#define	MSR_IA32_MC23_STATUS 0x0000045D

#define	MSR_IA32_MC24_STATUS 0x00000461

#define	MSR_IA32_MC25_STATUS 0x00000465

#define	MSR_IA32_MC26_STATUS 0x00000469

#define	MSR_IA32_MC27_STATUS 0x0000046D

#define	MSR_IA32_MC28_STATUS 0x00000471


#define	MSR_IA32_MC0_ADDR 0x00000402

#define	MSR_IA32_MC1_ADDR 0x00000406

#define	MSR_IA32_MC2_ADDR 0x0000040A

#define	MSR_IA32_MC3_ADDR 0x0000040E

#define	MSR_IA32_MC4_ADDR 0x00000412

#define	MSR_IA32_MC5_ADDR 0x00000416

#define	MSR_IA32_MC6_ADDR 0x0000041A

#define	MSR_IA32_MC7_ADDR 0x0000041E

#define	MSR_IA32_MC8_ADDR 0x00000422

#define	MSR_IA32_MC9_ADDR 0x00000426

#define	MSR_IA32_MC10_ADDR 0x0000042A

#define	MSR_IA32_MC11_ADDR 0x0000042E

#define	MSR_IA32_MC12_ADDR 0x00000432

#define	MSR_IA32_MC13_ADDR 0x00000436

#define	MSR_IA32_MC14_ADDR 0x0000043A

#define	MSR_IA32_MC15_ADDR 0x0000043E

#define	MSR_IA32_MC16_ADDR 0x00000442

#define	MSR_IA32_MC17_ADDR 0x00000446

#define	MSR_IA32_MC18_ADDR 0x0000044A

#define	MSR_IA32_MC19_ADDR 0x0000044E

#define	MSR_IA32_MC20_ADDR 0x00000452

#define	MSR_IA32_MC21_ADDR 0x00000456

#define	MSR_IA32_MC22_ADDR 0x0000045A

#define	MSR_IA32_MC23_ADDR 0x0000045E

#define	MSR_IA32_MC24_ADDR 0x00000462

#define	MSR_IA32_MC25_ADDR 0x00000466

#define	MSR_IA32_MC26_ADDR 0x0000046A

#define	MSR_IA32_MC27_ADDR 0x0000046E

#define	MSR_IA32_MC28_ADDR 0x00000472


#define	MSR_IA32_MC0_MISC 0x00000403

#define	MSR_IA32_MC1_MISC 0x00000407

#define	MSR_IA32_MC2_MISC 0x0000040B

#define	MSR_IA32_MC3_MISC 0x0000040F

#define	MSR_IA32_MC4_MISC 0x00000413

#define	MSR_IA32_MC5_MISC 0x00000417

#define	MSR_IA32_MC6_MISC 0x0000041B

#define	MSR_IA32_MC7_MISC 0x0000041F

#define	MSR_IA32_MC8_MISC 0x00000423

#define	MSR_IA32_MC9_MISC 0x00000427

#define	MSR_IA32_MC10_MISC 0x0000042B

#define	MSR_IA32_MC11_MISC 0x0000042F

#define	MSR_IA32_MC12_MISC 0x00000433

#define	MSR_IA32_MC13_MISC 0x00000437

#define	MSR_IA32_MC14_MISC 0x0000043B

#define	MSR_IA32_MC15_MISC 0x0000043F

#define	MSR_IA32_MC16_MISC 0x00000443

#define	MSR_IA32_MC17_MISC 0x00000447

#define	MSR_IA32_MC18_MISC 0x0000044B

#define	MSR_IA32_MC19_MISC 0x0000044F

#define	MSR_IA32_MC20_MISC 0x00000453

#define	MSR_IA32_MC21_MISC 0x00000457

#define	MSR_IA32_MC22_MISC 0x0000045B

#define	MSR_IA32_MC23_MISC 0x0000045F

#define	MSR_IA32_MC24_MISC 0x00000463

#define	MSR_IA32_MC25_MISC 0x00000467

#define	MSR_IA32_MC26_MISC 0x0000046B

#define	MSR_IA32_MC27_MISC 0x0000046F

#define	MSR_IA32_MC28_MISC 0x00000473


#define	MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00

#define	MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06


#define	MSR_IA32_A_PMC0 0x000004C1

#define	MSR_IA32_A_PMC1 0x000004C2

#define	MSR_IA32_A_PMC2 0x000004C3

#define	MSR_IA32_A_PMC3 0x000004C4

#define	MSR_IA32_A_PMC4 0x000004C5

#define	MSR_IA32_A_PMC5 0x000004C6

#define	MSR_IA32_A_PMC6 0x000004C7

#define	MSR_IA32_A_PMC7 0x000004C8


#define	MSR_IA32_RTIT_ADDR0_A 0x00000580

#define	MSR_IA32_RTIT_ADDR1_A 0x00000582

#define	MSR_IA32_RTIT_ADDR2_A 0x00000584

#define	MSR_IA32_RTIT_ADDR3_A 0x00000586


#define	MSR_IA32_RTIT_ADDR0_B 0x00000581

#define	MSR_IA32_RTIT_ADDR1_B 0x00000583

#define	MSR_IA32_RTIT_ADDR2_B 0x00000585

#define	MSR_IA32_RTIT_ADDR3_B 0x00000587


#define	MSR_IA32_X2APIC_ISR0 0x00000810

#define	MSR_IA32_X2APIC_ISR1 0x00000811

#define	MSR_IA32_X2APIC_ISR2 0x00000812

#define	MSR_IA32_X2APIC_ISR3 0x00000813

#define	MSR_IA32_X2APIC_ISR4 0x00000814

#define	MSR_IA32_X2APIC_ISR5 0x00000815

#define	MSR_IA32_X2APIC_ISR6 0x00000816

#define	MSR_IA32_X2APIC_ISR7 0x00000817


#define	MSR_IA32_X2APIC_TMR0 0x00000818

#define	MSR_IA32_X2APIC_TMR1 0x00000819

#define	MSR_IA32_X2APIC_TMR2 0x0000081A

#define	MSR_IA32_X2APIC_TMR3 0x0000081B

#define	MSR_IA32_X2APIC_TMR4 0x0000081C

#define	MSR_IA32_X2APIC_TMR5 0x0000081D

#define	MSR_IA32_X2APIC_TMR6 0x0000081E

#define	MSR_IA32_X2APIC_TMR7 0x0000081F


#define	MSR_IA32_X2APIC_IRR0 0x00000820

#define	MSR_IA32_X2APIC_IRR1 0x00000821

#define	MSR_IA32_X2APIC_IRR2 0x00000822

#define	MSR_IA32_X2APIC_IRR3 0x00000823

#define	MSR_IA32_X2APIC_IRR4 0x00000824

#define	MSR_IA32_X2APIC_IRR5 0x00000825

#define	MSR_IA32_X2APIC_IRR6 0x00000826

#define	MSR_IA32_X2APIC_IRR7 0x00000827

Enumerations
enum	RTIT_TOPA_MEMORY_SIZE { RtitTopaMemorySize4K = 0, RtitTopaMemorySize8K, RtitTopaMemorySize16K, RtitTopaMemorySize32K, RtitTopaMemorySize64K, RtitTopaMemorySize128K, RtitTopaMemorySize256K, RtitTopaMemorySize512K, RtitTopaMemorySize1M, RtitTopaMemorySize2M, RtitTopaMemorySize4M, RtitTopaMemorySize8M, RtitTopaMemorySize16M, RtitTopaMemorySize32M, RtitTopaMemorySize64M, RtitTopaMemorySize128M }

Detailed Description

Intel Architectural MSR Definitions.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define MSR_IA32_A_PMC0 0x000004C1

Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) && IA32_PERF_CAPABILITIES[ 13] = 1.

Parameters

ECX	MSR_IA32_A_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);

Note: MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM. MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM. MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM. MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM. MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM. MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM. MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM. MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.

#define MSR_IA32_A_PMC1 0x000004C2

Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) && IA32_PERF_CAPABILITIES[ 13] = 1.

Parameters

ECX	MSR_IA32_A_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);

Note: MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM. MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM. MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM. MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM. MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM. MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM. MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM. MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.

#define MSR_IA32_A_PMC2 0x000004C3

Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) && IA32_PERF_CAPABILITIES[ 13] = 1.

Parameters

ECX	MSR_IA32_A_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);

Note: MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM. MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM. MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM. MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM. MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM. MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM. MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM. MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.

#define MSR_IA32_A_PMC3 0x000004C4

Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) && IA32_PERF_CAPABILITIES[ 13] = 1.

Parameters

ECX	MSR_IA32_A_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);

Note: MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM. MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM. MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM. MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM. MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM. MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM. MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM. MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.

#define MSR_IA32_A_PMC4 0x000004C5

Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) && IA32_PERF_CAPABILITIES[ 13] = 1.

Parameters

ECX	MSR_IA32_A_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);

Note: MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM. MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM. MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM. MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM. MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM. MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM. MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM. MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.

#define MSR_IA32_A_PMC5 0x000004C6

Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) && IA32_PERF_CAPABILITIES[ 13] = 1.

Parameters

ECX	MSR_IA32_A_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);

Note: MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM. MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM. MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM. MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM. MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM. MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM. MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM. MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.

#define MSR_IA32_A_PMC6 0x000004C7

Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) && IA32_PERF_CAPABILITIES[ 13] = 1.

Parameters

ECX	MSR_IA32_A_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);

Note: MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM. MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM. MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM. MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM. MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM. MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM. MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM. MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.

#define MSR_IA32_A_PMC7 0x000004C8

Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) && IA32_PERF_CAPABILITIES[ 13] = 1.

Parameters

ECX	MSR_IA32_A_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);

Note: MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM. MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM. MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM. MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM. MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM. MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM. MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM. MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.

#define MSR_IA32_APERF 0x000000E8

Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =

C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at the coordinated clock frequency, when the logical processor is in C0. Cleared upon overflow / wrap-around of IA32_MPERF.

Parameters

ECX	MSR_IA32_APERF (0x000000E8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_APERF);
AsmWriteMsr64 (MSR_IA32_APERF, Msr);

Note: MSR_IA32_APERF is defined as IA32_APERF in SDM.

#define MSR_IA32_APIC_BASE 0x0000001B

06_01H.

Parameters

ECX	MSR_IA32_APIC_BASE (0x0000001B)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_APIC_BASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_APIC_BASE_REGISTER.

Example usage

MSR_IA32_APIC_BASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);

Note: MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.

#define MSR_IA32_BIOS_SIGN_ID 0x0000008B

BIOS Update Signature (RO) Returns the microcode update signature following the execution of CPUID.01H. A processor may prevent writing to this MSR when loading guest states on VM entries or saving guest states on VM exits. Introduced at Display Family / Display Model 06_01H.

Parameters

ECX	MSR_IA32_BIOS_SIGN_ID (0x0000008B)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.

Example usage

MSR_IA32_BIOS_SIGN_ID_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);

Note: MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.

#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079

BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a microcode update to be loaded into the processor. See Section 9.11.6, "Microcode Update Loader." A processor may prevent writing to this MSR when loading guest states on VM entries or saving guest states on VM exits. Introduced at Display Family / Display Model 06_01H.

Parameters

ECX	MSR_IA32_BIOS_UPDT_TRIG (0x00000079)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = 0;
AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);

Note: MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.

#define MSR_IA32_BNDCFGS 0x00000D90

Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H, ECX=0H):EBX[14] = 1).

Parameters

ECX	MSR_IA32_BNDCFGS (0x00000D90)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_BNDCFGS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_BNDCFGS_REGISTER.

Example usage

MSR_IA32_BNDCFGS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);
AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);

Note: MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.

#define MSR_IA32_CLOCK_MODULATION 0x0000019A

Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled Clock Modulation.". If CPUID.01H:EDX[22] = 1.

Parameters

ECX	MSR_IA32_CLOCK_MODULATION (0x0000019A)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.

Example usage

MSR_IA32_CLOCK_MODULATION_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);

Note: MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.

#define MSR_IA32_CPU_DCA_CAP 0x000001F9

If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.

Parameters

ECX	MSR_IA32_CPU_DCA_CAP (0x000001F9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);
AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);

Note: MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.

#define MSR_IA32_CSTAR 0xC0000083

IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL instruction is not recognized in compatibility mode. If CPUID.80000001:EDX.[29] = 1.

Parameters

ECX	MSR_IA32_CSTAR (0xC0000083)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_CSTAR);
AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);

Note: MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.

#define MSR_IA32_DCA_0_CAP 0x000001FA

DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.

Parameters

ECX	MSR_IA32_DCA_0_CAP (0x000001FA)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_DCA_0_CAP_REGISTER.

Example usage

MSR_IA32_DCA_0_CAP_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);
AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);

Note: MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.

#define MSR_IA32_DEBUG_INTERFACE 0x00000C80

Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.

Parameters

ECX	MSR_IA32_DEBUG_INTERFACE (0x00000C80)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.

Example usage

MSR_IA32_DEBUG_INTERFACE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);

Note: MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.

#define MSR_IA32_DEBUGCTL 0x000001D9

Trace/Profile Resource Control (R/W). Introduced at Display Family / Display Model 06_0EH.

Parameters

ECX	MSR_IA32_DEBUGCTL (0x000001D9)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_DEBUGCTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_DEBUGCTL_REGISTER.

Example usage

MSR_IA32_DEBUGCTL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);

Note: MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.

#define MSR_IA32_DS_AREA 0x00000600

DS Save Area (R/W) Points to the linear address of the first byte of the DS buffer management area, which is used to manage the BTS and PEBS buffers. See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS buffer management area, if IA-32e mode is active.

Parameters

ECX	MSR_IA32_DS_AREA (0x00000600)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_DS_AREA_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_DS_AREA_REGISTER.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);
AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);

Note: MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.

#define MSR_IA32_EFER 0xC0000080

Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0] CPUID.80000001H:EDX.[2 9]).

Parameters

ECX	MSR_IA32_EFER (0xC0000080)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_EFER_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_EFER_REGISTER.

Example usage

MSR_IA32_EFER_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);

Note: MSR_IA32_EFER is defined as IA32_EFER in SDM.

#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0

Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.

Parameters

ECX	MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.

Example usage

MSR_IA32_ENERGY_PERF_BIAS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);
AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);

Note: MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.

#define MSR_IA32_FEATURE_CONTROL 0x0000003A

Control Features in Intel 64 Processor (R/W). If any one enumeration condition for defined bit field holds.

Parameters

ECX	MSR_IA32_FEATURE_CONTROL (0x0000003A)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.

Example usage

MSR_IA32_FEATURE_CONTROL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);

Note: MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.

#define MSR_IA32_FIXED_CTR0 0x00000309

Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If CPUID.0AH: EDX[4:0] > 0.

Parameters

ECX	MSR_IA32_FIXED_CTR0 (0x00000309)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);
AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);

Note: MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.

#define MSR_IA32_FIXED_CTR1 0x0000030A

Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If CPUID.0AH: EDX[4:0] > 1.

Parameters

ECX	MSR_IA32_FIXED_CTR1 (0x0000030A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);
AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);

Note: MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.

#define MSR_IA32_FIXED_CTR2 0x0000030B

Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If CPUID.0AH: EDX[4:0] > 2.

Parameters

ECX	MSR_IA32_FIXED_CTR2 (0x0000030B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);
AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);

Note: MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.

#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D

Fixed-Function Performance Counter Control (R/W) Counter increments while the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]

1.

Parameters

ECX	MSR_IA32_FIXED_CTR_CTRL (0x0000038D)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.

Example usage

MSR_IA32_FIXED_CTR_CTRL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);
AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);

Note: MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.

#define MSR_IA32_FMASK 0xC0000084

System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.

Parameters

ECX	MSR_IA32_FMASK (0xC0000084)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_FMASK);
AsmWriteMsr64 (MSR_IA32_FMASK, Msr);

Note: MSR_IA32_FMASK is defined as IA32_FMASK in SDM.

#define MSR_IA32_FS_BASE 0xC0000100

Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.

Parameters

ECX	MSR_IA32_FS_BASE (0xC0000100)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);
AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);

Note: MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.

#define MSR_IA32_GS_BASE 0xC0000101

Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.

Parameters

ECX	MSR_IA32_GS_BASE (0xC0000101)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);
AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);

Note: MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.

#define MSR_IA32_HWP_CAPABILITIES 0x00000771

HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.

Parameters

ECX	MSR_IA32_HWP_CAPABILITIES (0x00000771)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.

Example usage

MSR_IA32_HWP_CAPABILITIES_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);

Note: MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.

#define MSR_IA32_HWP_INTERRUPT 0x00000773

Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.

Parameters

ECX	MSR_IA32_HWP_INTERRUPT (0x00000773)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.

Example usage

MSR_IA32_HWP_INTERRUPT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);
AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);

Note: MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.

#define MSR_IA32_HWP_REQUEST 0x00000774

Power Management Control Hints to a Logical Processor (R/W). If CPUID.06H:EAX.[7] = 1.

Parameters

ECX	MSR_IA32_HWP_REQUEST (0x00000774)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_HWP_REQUEST_REGISTER.

Example usage

MSR_IA32_HWP_REQUEST_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);
AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);

Note: MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.

#define MSR_IA32_HWP_REQUEST_PKG 0x00000772

Power Management Control Hints for All Logical Processors in a Package (R/W). If CPUID.06H:EAX.[11] = 1.

Parameters

ECX	MSR_IA32_HWP_REQUEST_PKG (0x00000772)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.

Example usage

MSR_IA32_HWP_REQUEST_PKG_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);
AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);

Note: MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.

#define MSR_IA32_HWP_STATUS 0x00000777

Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If CPUID.06H:EAX.[7] = 1.

Parameters

ECX	MSR_IA32_HWP_STATUS (0x00000777)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_HWP_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_HWP_STATUS_REGISTER.

Example usage

MSR_IA32_HWP_STATUS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);
AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);

Note: MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.

#define MSR_IA32_KERNEL_GS_BASE 0xC0000102

Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.

Parameters

ECX	MSR_IA32_KERNEL_GS_BASE (0xC0000102)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);
AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);

Note: MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.

#define MSR_IA32_L2_QOS_CFG 0x00000C82

L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).

Parameters

ECX	MSR_IA32_L2_QOS_CFG (0x00000C82)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.

Example usage

MSR_IA32_L2_QOS_CFG_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);
AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);

Note: MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.

#define MSR_IA32_L3_QOS_CFG 0x00000C81

L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).

Parameters

ECX	MSR_IA32_L3_QOS_CFG (0x00000C81)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.

Example usage

MSR_IA32_L3_QOS_CFG_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);
AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);

Note: MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.

#define MSR_IA32_LSTAR 0xC0000082

IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.

Parameters

ECX	MSR_IA32_LSTAR (0xC0000082)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_LSTAR);
AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);

Note: MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.

#define MSR_IA32_MC0_ADDR 0x00000402

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC0_CTL 0x00000400

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC0_CTL2 0x00000280

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC0_MISC 0x00000403

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC0_STATUS 0x00000401

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC10_ADDR 0x0000042A

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC10_CTL 0x00000428

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC10_CTL2 0x0000028A

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC10_MISC 0x0000042B

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC10_STATUS 0x00000429

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC11_ADDR 0x0000042E

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC11_CTL 0x0000042C

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC11_CTL2 0x0000028B

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC11_MISC 0x0000042F

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC11_STATUS 0x0000042D

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC12_ADDR 0x00000432

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC12_CTL 0x00000430

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC12_CTL2 0x0000028C

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC12_MISC 0x00000433

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC12_STATUS 0x00000431

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC13_ADDR 0x00000436

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC13_CTL 0x00000434

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC13_CTL2 0x0000028D

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC13_MISC 0x00000437

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC13_STATUS 0x00000435

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC14_ADDR 0x0000043A

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC14_CTL 0x00000438

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC14_CTL2 0x0000028E

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC14_MISC 0x0000043B

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC14_STATUS 0x00000439

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC15_ADDR 0x0000043E

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC15_CTL 0x0000043C

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC15_CTL2 0x0000028F

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC15_MISC 0x0000043F

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC15_STATUS 0x0000043D

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC16_ADDR 0x00000442

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC16_CTL 0x00000440

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC16_CTL2 0x00000290

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC16_MISC 0x00000443

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC16_STATUS 0x00000441

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC17_ADDR 0x00000446

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC17_CTL 0x00000444

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC17_CTL2 0x00000291

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC17_MISC 0x00000447

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC17_STATUS 0x00000445

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC18_ADDR 0x0000044A

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC18_CTL 0x00000448

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC18_CTL2 0x00000292

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC18_MISC 0x0000044B

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC18_STATUS 0x00000449

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC19_ADDR 0x0000044E

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC19_CTL 0x0000044C

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC19_CTL2 0x00000293

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC19_MISC 0x0000044F

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC19_STATUS 0x0000044D

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC1_ADDR 0x00000406

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC1_CTL 0x00000404

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC1_CTL2 0x00000281

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC1_MISC 0x00000407

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC1_STATUS 0x00000405

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC20_ADDR 0x00000452

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC20_CTL 0x00000450

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC20_CTL2 0x00000294

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC20_MISC 0x00000453

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC20_STATUS 0x00000451

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC21_ADDR 0x00000456

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC21_CTL 0x00000454

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC21_CTL2 0x00000295

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC21_MISC 0x00000457

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC21_STATUS 0x00000455

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC22_ADDR 0x0000045A

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC22_CTL 0x00000458

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC22_CTL2 0x00000296

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC22_MISC 0x0000045B

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC22_STATUS 0x00000459

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC23_ADDR 0x0000045E

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC23_CTL 0x0000045C

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC23_CTL2 0x00000297

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC23_MISC 0x0000045F

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC23_STATUS 0x0000045D

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC24_ADDR 0x00000462

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC24_CTL 0x00000460

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC24_CTL2 0x00000298

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC24_MISC 0x00000463

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC24_STATUS 0x00000461

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC25_ADDR 0x00000466

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC25_CTL 0x00000464

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC25_CTL2 0x00000299

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC25_MISC 0x00000467

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC25_STATUS 0x00000465

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC26_ADDR 0x0000046A

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC26_CTL 0x00000468

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC26_CTL2 0x0000029A

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC26_MISC 0x0000046B

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC26_STATUS 0x00000469

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC27_ADDR 0x0000046E

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC27_CTL 0x0000046C

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC27_CTL2 0x0000029B

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC27_MISC 0x0000046F

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC27_STATUS 0x0000046D

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC28_ADDR 0x00000472

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC28_CTL 0x00000470

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC28_CTL2 0x0000029C

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC28_MISC 0x00000473

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC28_STATUS 0x00000471

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC29_CTL2 0x0000029D

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC2_ADDR 0x0000040A

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC2_CTL 0x00000408

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC2_CTL2 0x00000282

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC2_MISC 0x0000040B

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC2_STATUS 0x00000409

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC30_CTL2 0x0000029E

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC31_CTL2 0x0000029F

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC3_ADDR 0x0000040E

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC3_CTL 0x0000040C

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC3_CTL2 0x00000283

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC3_MISC 0x0000040F

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC3_STATUS 0x0000040D

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC4_ADDR 0x00000412

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC4_CTL 0x00000410

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC4_CTL2 0x00000284

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC4_MISC 0x00000413

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC4_STATUS 0x00000411

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC5_ADDR 0x00000416

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC5_CTL 0x00000414

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC5_CTL2 0x00000285

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC5_MISC 0x00000417

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC5_STATUS 0x00000415

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC6_ADDR 0x0000041A

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC6_CTL 0x00000418

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC6_CTL2 0x00000286

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC6_MISC 0x0000041B

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC6_STATUS 0x00000419

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC7_ADDR 0x0000041E

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC7_CTL 0x0000041C

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC7_CTL2 0x00000287

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC7_MISC 0x0000041F

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC7_STATUS 0x0000041D

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC8_ADDR 0x00000422

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC8_CTL 0x00000420

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC8_CTL2 0x00000288

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC8_MISC 0x00000423

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC8_STATUS 0x00000421

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MC9_ADDR 0x00000426

MCn_ADDR. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);

Note: MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.

#define MSR_IA32_MC9_CTL 0x00000424

MCn_CTL. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);

Note: MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.

#define MSR_IA32_MC9_CTL2 0x00000289

Provides the programming interface to use corrected MC error signaling capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.

Parameters

ECX	MSR_IA32_MCn_CTL2
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MC_CTL2_REGISTER.

Example usage

MSR_IA32_MC_CTL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);

Note: MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.

#define MSR_IA32_MC9_MISC 0x00000427

MCn_MISC. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);

Note: MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.

#define MSR_IA32_MC9_STATUS 0x00000425

MCn_STATUS. If IA32_MCG_CAP.CNT > n.

Parameters

ECX	MSR_IA32_MCn_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);

Note: MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.

#define MSR_IA32_MCG_CAP 0x00000179

Global Machine Check Capability (RO). Introduced at Display Family / Display Model 06_01H.

Parameters

ECX	MSR_IA32_MCG_CAP (0x00000179)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MCG_CAP_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MCG_CAP_REGISTER.

Example usage

MSR_IA32_MCG_CAP_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);

Note: MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.

#define MSR_IA32_MCG_CTL 0x0000017B

Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.

Parameters

ECX	MSR_IA32_MCG_CTL (0x0000017B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);
AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);

Note: MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.

#define MSR_IA32_MCG_EXT_CTL 0x000004D0

(R/W). If IA32_MCG_CAP.LMCE_P =1.

Parameters

ECX	MSR_IA32_MCG_EXT_CTL (0x000004D0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.

Example usage

MSR_IA32_MCG_EXT_CTL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);

Note: MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.

#define MSR_IA32_MCG_STATUS 0x0000017A

Global Machine Check Status (R/W0). Introduced at Display Family / Display Model 06_01H.

Parameters

ECX	MSR_IA32_MCG_STATUS (0x0000017A)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MCG_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MCG_STATUS_REGISTER.

Example usage

MSR_IA32_MCG_STATUS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);

Note: MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.

#define MSR_IA32_MISC_ENABLE 0x000001A0

Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.

Parameters

ECX	MSR_IA32_MISC_ENABLE (0x000001A0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MISC_ENABLE_REGISTER.

Example usage

MSR_IA32_MISC_ENABLE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);

Note: MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.

#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006

See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced at Display Family / Display Model 0F_03H.

Parameters

ECX	MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);

Note: MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.

#define MSR_IA32_MPERF 0x000000E7

TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1. C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative to TSC freq.) when the logical processor is in C0. Cleared upon overflow / wrap-around of IA32_APERF.

Parameters

ECX	MSR_IA32_MPERF (0x000000E7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MPERF);
AsmWriteMsr64 (MSR_IA32_MPERF, Msr);

Note: MSR_IA32_MPERF is defined as IA32_MPERF in SDM.

#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF

MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.

Parameters

ECX	MSR_IA32_MTRR_DEF_TYPE (0x000002FF)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.

Example usage

MSR_IA32_MTRR_DEF_TYPE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);

Note: MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.

#define MSR_IA32_MTRR_FIX16K_80000 0x00000258

MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.

Parameters

ECX	MSR_IA32_MTRR_FIX16K_80000 (0x00000258)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);
AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);

Note: MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.

#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259

MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.

Parameters

ECX	MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);
AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);

Note: MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.

#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268

See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.

Parameters

ECX	MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);

Note: MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.

#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269

MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.

Parameters

ECX	MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);

Note: MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.

#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A

MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.

Parameters

ECX	MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);

Note: MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.

#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B

MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.

Parameters

ECX	MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);

Note: MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.

#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C

MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.

Parameters

ECX	MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);

Note: MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.

#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D

MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.

Parameters

ECX	MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);

Note: MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.

#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E

MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.

Parameters

ECX	MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);

Note: MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.

#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F

MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.

Parameters

ECX	MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);

Note: MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.

#define MSR_IA32_MTRR_FIX64K_00000 0x00000250

MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.

Parameters

ECX	MSR_IA32_MTRR_FIX64K_00000 (0x00000250)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);
AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);

Note: MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.

#define MSR_IA32_MTRR_PHYSBASE0 0x00000200

MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSBASEn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSBASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.

#define MSR_IA32_MTRR_PHYSBASE1 0x00000202

MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSBASEn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSBASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.

#define MSR_IA32_MTRR_PHYSBASE2 0x00000204

MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSBASEn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSBASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.

#define MSR_IA32_MTRR_PHYSBASE3 0x00000206

MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSBASEn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSBASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.

#define MSR_IA32_MTRR_PHYSBASE4 0x00000208

MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSBASEn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSBASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.

#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A

MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSBASEn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSBASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.

#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C

MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSBASEn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSBASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.

#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E

MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSBASEn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSBASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.

#define MSR_IA32_MTRR_PHYSBASE8 0x00000210

MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSBASEn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSBASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.

#define MSR_IA32_MTRR_PHYSBASE9 0x00000212

MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSBASEn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSBASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.

#define MSR_IA32_MTRR_PHYSMASK0 0x00000201

MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSMASKn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSMASK_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.

#define MSR_IA32_MTRR_PHYSMASK1 0x00000203

MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSMASKn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSMASK_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.

#define MSR_IA32_MTRR_PHYSMASK2 0x00000205

MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSMASKn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSMASK_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.

#define MSR_IA32_MTRR_PHYSMASK3 0x00000207

MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSMASKn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSMASK_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.

#define MSR_IA32_MTRR_PHYSMASK4 0x00000209

MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSMASKn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSMASK_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.

#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B

MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSMASKn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSMASK_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.

#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D

MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSMASKn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSMASK_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.

#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F

MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSMASKn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSMASK_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.

#define MSR_IA32_MTRR_PHYSMASK8 0x00000211

MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSMASKn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSMASK_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.

#define MSR_IA32_MTRR_PHYSMASK9 0x00000213

MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.

Parameters

ECX	MSR_IA32_MTRR_PHYSMASKn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.

Example usage

MSR_IA32_MTRR_PHYSMASK_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);

Note: MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.

#define MSR_IA32_MTRRCAP 0x000000FE

MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.". Introduced at Display Family / Display Model 06_01H.

Parameters

ECX	MSR_IA32_MTRRCAP (0x000000FE)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_MTRRCAP_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_MTRRCAP_REGISTER.

Example usage

MSR_IA32_MTRRCAP_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);

Note: MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.

#define MSR_IA32_P5_MC_ADDR 0x00000000

See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).

Parameters

ECX	MSR_IA32_P5_MC_ADDR (0x00000000)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);

Note: MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.

#define MSR_IA32_P5_MC_TYPE 0x00000001

See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.

Parameters

ECX	MSR_IA32_P5_MC_TYPE (0x00000001)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);

Note: MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.

#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2

Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of an interrupt on temperature transitions detected with the package's thermal sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H: EAX[6] = 1.

Parameters

ECX	MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.

Example usage

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);
AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);

Note: MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.

#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1

Package Thermal Status Information (RO) Contains status information about the package's thermal sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H: EAX[6] = 1.

Parameters

ECX	MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.

Example usage

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);

Note: MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.

#define MSR_IA32_PAT 0x00000277

IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.

Parameters

ECX	MSR_IA32_PAT (0x00000277)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PAT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PAT_REGISTER.

Example usage

MSR_IA32_PAT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);
AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);

Note: MSR_IA32_PAT is defined as IA32_PAT in SDM.

#define MSR_IA32_PEBS_ENABLE 0x000003F1

PEBS Control (R/W).

Parameters

ECX	MSR_IA32_PEBS_ENABLE (0x000003F1)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.

Example usage

MSR_IA32_PEBS_ENABLE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);
AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);

Note: MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.

#define MSR_IA32_PERF_CAPABILITIES 0x00000345

RO. If CPUID.01H: ECX[15] = 1.

Parameters

ECX	MSR_IA32_PERF_CAPABILITIES (0x00000345)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.

Example usage

MSR_IA32_PERF_CAPABILITIES_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);
AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);

Note: MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.

#define MSR_IA32_PERF_CTL 0x00000199

(R/W). Introduced at Display Family / Display Model 0F_03H.

Parameters

ECX	MSR_IA32_PERF_CTL (0x00000199)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PERF_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PERF_CTL_REGISTER.

Example usage

MSR_IA32_PERF_CTL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);
AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);

Note: MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.

#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F

Global Performance Counter Control (R/W) Counter increments while the result of ANDing respective enable bit in this MSR with the corresponding OS or USR bits in the general-purpose or fixed counter control MSR is true. If CPUID.0AH: EAX[7:0] > 0.

Parameters

ECX	MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.

Example usage

MSR_IA32_PERF_GLOBAL_CTRL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);
AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);

Note: MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.

#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392

Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] > 3.

Parameters

ECX	MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.

Example usage

MSR_IA32_PERF_GLOBAL_INUSE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);

Note: MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.

#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390

Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] > 0 && CPUID.0AH: EAX[7:0] <= 3.

Parameters

ECX	MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.

Example usage

MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);
AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);

Note: MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.

#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E

Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.

Parameters

ECX	MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.

Example usage

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);

Note: MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.

#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390

Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH: EAX[7:0] > 3.

Parameters

ECX	MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.

Example usage

MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);
AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);

Note: MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.

#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391

Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH: EAX[7:0] > 3.

Parameters

ECX	MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.

Example usage

MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);
AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);

Note: MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.

#define MSR_IA32_PERF_STATUS 0x00000198

Current performance state(P-State) operating point (RO). Introduced at Display Family / Display Model 0F_03H.

Parameters

ECX	MSR_IA32_PERF_STATUS (0x00000198)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PERF_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PERF_STATUS_REGISTER.

Example usage

MSR_IA32_PERF_STATUS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);

Note: MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.

#define MSR_IA32_PERFEVTSEL0 0x00000186

Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.

Parameters

ECX	MSR_IA32_PERFEVTSELn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PERFEVTSEL_REGISTER.

Example usage

MSR_IA32_PERFEVTSEL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);

Note: MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM. MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.

#define MSR_IA32_PERFEVTSEL1 0x00000187

Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.

Parameters

ECX	MSR_IA32_PERFEVTSELn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PERFEVTSEL_REGISTER.

Example usage

MSR_IA32_PERFEVTSEL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);

Note: MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM. MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.

#define MSR_IA32_PERFEVTSEL2 0x00000188

Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.

Parameters

ECX	MSR_IA32_PERFEVTSELn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PERFEVTSEL_REGISTER.

Example usage

MSR_IA32_PERFEVTSEL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);

Note: MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM. MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.

#define MSR_IA32_PERFEVTSEL3 0x00000189

Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.

Parameters

ECX	MSR_IA32_PERFEVTSELn
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PERFEVTSEL_REGISTER.

Example usage

MSR_IA32_PERFEVTSEL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);

Note: MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM. MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.

#define MSR_IA32_PKG_HDC_CTL 0x00000DB0

Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.

Parameters

ECX	MSR_IA32_PKG_HDC_CTL (0x00000DB0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.

Example usage

MSR_IA32_PKG_HDC_CTL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);
AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);

Note: MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.

#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8

DCA Capability (R). If CPUID.01H: ECX[18] = 1.

Parameters

ECX	MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);

Note: MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.

#define MSR_IA32_PLATFORM_ID 0x00000017

Platform ID (RO) The operating system can use this MSR to determine "slot" information for the processor and the proper microcode update to load. Introduced at Display Family / Display Model 06_01H.

Parameters

ECX	MSR_IA32_PLATFORM_ID (0x00000017)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PLATFORM_ID_REGISTER.

Example usage

MSR_IA32_PLATFORM_ID_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);

Note: MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.

#define MSR_IA32_PM_CTL1 0x00000DB1

Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.

Parameters

ECX	MSR_IA32_PM_CTL1 (0x00000DB1)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PM_CTL1_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PM_CTL1_REGISTER.

Example usage

MSR_IA32_PM_CTL1_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);
AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);

Note: MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.

#define MSR_IA32_PM_ENABLE 0x00000770

Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.

Parameters

ECX	MSR_IA32_PM_ENABLE (0x00000770)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PM_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PM_ENABLE_REGISTER.

Example usage

MSR_IA32_PM_ENABLE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);
AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);

Note: MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.

#define MSR_IA32_PMC0 0x000000C1

General Performance Counters (R/W). MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.

Parameters

ECX	MSR_IA32_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_PMC0);
AsmWriteMsr64 (MSR_IA32_PMC0, Msr);

Note: MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM. MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM. MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM. MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM. MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM. MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM. MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM. MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.

#define MSR_IA32_PMC1 0x000000C2

General Performance Counters (R/W). MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.

Parameters

ECX	MSR_IA32_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_PMC0);
AsmWriteMsr64 (MSR_IA32_PMC0, Msr);

Note: MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM. MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM. MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM. MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM. MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM. MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM. MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM. MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.

#define MSR_IA32_PMC2 0x000000C3

General Performance Counters (R/W). MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.

Parameters

ECX	MSR_IA32_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_PMC0);
AsmWriteMsr64 (MSR_IA32_PMC0, Msr);

Note: MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM. MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM. MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM. MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM. MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM. MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM. MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM. MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.

#define MSR_IA32_PMC3 0x000000C4

General Performance Counters (R/W). MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.

Parameters

ECX	MSR_IA32_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_PMC0);
AsmWriteMsr64 (MSR_IA32_PMC0, Msr);

Note: MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM. MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM. MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM. MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM. MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM. MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM. MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM. MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.

#define MSR_IA32_PMC4 0x000000C5

General Performance Counters (R/W). MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.

Parameters

ECX	MSR_IA32_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_PMC0);
AsmWriteMsr64 (MSR_IA32_PMC0, Msr);

Note: MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM. MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM. MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM. MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM. MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM. MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM. MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM. MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.

#define MSR_IA32_PMC5 0x000000C6

General Performance Counters (R/W). MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.

Parameters

ECX	MSR_IA32_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_PMC0);
AsmWriteMsr64 (MSR_IA32_PMC0, Msr);

Note: MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM. MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM. MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM. MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM. MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM. MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM. MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM. MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.

#define MSR_IA32_PMC6 0x000000C7

General Performance Counters (R/W). MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.

Parameters

ECX	MSR_IA32_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_PMC0);
AsmWriteMsr64 (MSR_IA32_PMC0, Msr);

Note: MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM. MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM. MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM. MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM. MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM. MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM. MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM. MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.

#define MSR_IA32_PMC7 0x000000C8

General Performance Counters (R/W). MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.

Parameters

ECX	MSR_IA32_PMCn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_PMC0);
AsmWriteMsr64 (MSR_IA32_PMC0, Msr);

Note: MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM. MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM. MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM. MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM. MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM. MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM. MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM. MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.

#define MSR_IA32_PQR_ASSOC 0x00000C8F

Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12] =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).

Parameters

ECX	MSR_IA32_PQR_ASSOC (0x00000C8F)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_PQR_ASSOC_REGISTER.

Example usage

MSR_IA32_PQR_ASSOC_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);
AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);

Note: MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.

#define MSR_IA32_QM_CTR 0x00000C8E

Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1 ).

Parameters

ECX	MSR_IA32_QM_CTR (0x00000C8E)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_QM_CTR_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_QM_CTR_REGISTER.

Example usage

MSR_IA32_QM_CTR_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);

Note: MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.

#define MSR_IA32_QM_EVTSEL 0x00000C8D

Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1 ).

Parameters

ECX	MSR_IA32_QM_EVTSEL (0x00000C8D)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_QM_EVTSEL_REGISTER.

Example usage

MSR_IA32_QM_EVTSEL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);
AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);

Note: MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.

#define MSR_IA32_RTIT_ADDR0_A 0x00000580

Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).

Parameters

ECX	MSR_IA32_RTIT_ADDRn_A
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.

Example usage

MSR_IA32_RTIT_ADDR_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);

Note: MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM. MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM. MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM. MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.

#define MSR_IA32_RTIT_ADDR0_B 0x00000581

Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).

Parameters

ECX	MSR_IA32_RTIT_ADDRn_B
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.

Example usage

MSR_IA32_RTIT_ADDR_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);

Note: MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM. MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM. MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM. MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.

#define MSR_IA32_RTIT_ADDR1_A 0x00000582

Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).

Parameters

ECX	MSR_IA32_RTIT_ADDRn_A
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.

Example usage

MSR_IA32_RTIT_ADDR_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);

Note: MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM. MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM. MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM. MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.

#define MSR_IA32_RTIT_ADDR1_B 0x00000583

Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).

Parameters

ECX	MSR_IA32_RTIT_ADDRn_B
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.

Example usage

MSR_IA32_RTIT_ADDR_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);

Note: MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM. MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM. MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM. MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.

#define MSR_IA32_RTIT_ADDR2_A 0x00000584

Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).

Parameters

ECX	MSR_IA32_RTIT_ADDRn_A
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.

Example usage

MSR_IA32_RTIT_ADDR_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);

Note: MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM. MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM. MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM. MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.

#define MSR_IA32_RTIT_ADDR2_B 0x00000585

Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).

Parameters

ECX	MSR_IA32_RTIT_ADDRn_B
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.

Example usage

MSR_IA32_RTIT_ADDR_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);

Note: MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM. MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM. MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM. MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.

#define MSR_IA32_RTIT_ADDR3_A 0x00000586

Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).

Parameters

ECX	MSR_IA32_RTIT_ADDRn_A
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.

Example usage

MSR_IA32_RTIT_ADDR_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);

Note: MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM. MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM. MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM. MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.

#define MSR_IA32_RTIT_ADDR3_B 0x00000587

Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).

Parameters

ECX	MSR_IA32_RTIT_ADDRn_B
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_RTIT_ADDR_REGISTER.

Example usage

MSR_IA32_RTIT_ADDR_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);

Note: MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM. MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM. MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM. MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.

#define MSR_IA32_RTIT_CR3_MATCH 0x00000572

Trace Filter CR3 Match Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).

Parameters

ECX	MSR_IA32_RTIT_CR3_MATCH (0x00000572)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.

Example usage

MSR_IA32_RTIT_CR3_MATCH_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);
AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);

Note: MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.

#define MSR_IA32_RTIT_CTL 0x00000570

Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).

Parameters

ECX	MSR_IA32_RTIT_CTL (0x00000570)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_RTIT_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_RTIT_CTL_REGISTER.

Example usage

MSR_IA32_RTIT_CTL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);

Note: MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.

#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560

Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).

Parameters

ECX	MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.

Example usage

MSR_IA32_RTIT_OUTPUT_BASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);

Note: MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.

#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561

Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).

Parameters

ECX	MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.

Example usage

MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);

Note: MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.

#define MSR_IA32_RTIT_STATUS 0x00000571

Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).

Parameters

ECX	MSR_IA32_RTIT_STATUS (0x00000571)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_RTIT_STATUS_REGISTER.

Example usage

MSR_IA32_RTIT_STATUS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);
AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);

Note: MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.

#define MSR_IA32_SGX_SVN_STATUS 0x00000500

Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.

Parameters

ECX	MSR_IA32_SGX_SVN_STATUS (0x00000500)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.

Example usage

MSR_IA32_SGX_SVN_STATUS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);

Note: MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.

#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C

IA32_SGXLEPUBKEYHASH(64*n+63):(64*n) Bits (64*n+63):(64*n) of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the default value is the digest of Intel's signing key. Read permitted If CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H): EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.

Parameters

ECX	MSR_IA32_SGXLEPUBKEYHASHn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);
AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);

Note: MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM. MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM. MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM. MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.

#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D

IA32_SGXLEPUBKEYHASH(64*n+63):(64*n) Bits (64*n+63):(64*n) of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the default value is the digest of Intel's signing key. Read permitted If CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H): EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.

Parameters

ECX	MSR_IA32_SGXLEPUBKEYHASHn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);
AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);

Note: MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM. MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM. MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM. MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.

#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E

IA32_SGXLEPUBKEYHASH(64*n+63):(64*n) Bits (64*n+63):(64*n) of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the default value is the digest of Intel's signing key. Read permitted If CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H): EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.

Parameters

ECX	MSR_IA32_SGXLEPUBKEYHASHn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);
AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);

Note: MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM. MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM. MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM. MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.

#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F

IA32_SGXLEPUBKEYHASH(64*n+63):(64*n) Bits (64*n+63):(64*n) of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the default value is the digest of Intel's signing key. Read permitted If CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H): EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.

Parameters

ECX	MSR_IA32_SGXLEPUBKEYHASHn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);
AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);

Note: MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM. MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM. MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM. MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.

#define MSR_IA32_SMBASE 0x0000009E

Base address of the logical processor's SMRAM image (RO, SMM only). If IA32_VMX_MISC[15].

Parameters

ECX	MSR_IA32_SMBASE (0x0000009E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_SMBASE);

Note: MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.

#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B

SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] = 1.

Parameters

ECX	MSR_IA32_SMM_MONITOR_CTL (0x0000009B)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.

Example usage

MSR_IA32_SMM_MONITOR_CTL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);

Note: MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.

#define MSR_IA32_SMRR_PHYSBASE 0x000001F2

SMRR Base Address (Writeable only in SMM) Base address of SMM memory range. If IA32_MTRRCAP.SMRR[11] = 1.

Parameters

ECX	MSR_IA32_SMRR_PHYSBASE (0x000001F2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.

Example usage

MSR_IA32_SMRR_PHYSBASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);
AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);

Note: MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.

#define MSR_IA32_SMRR_PHYSMASK 0x000001F3

SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If IA32_MTRRCAP[SMRR] = 1.

Parameters

ECX	MSR_IA32_SMRR_PHYSMASK (0x000001F3)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.

Example usage

MSR_IA32_SMRR_PHYSMASK_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);
AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);

Note: MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.

#define MSR_IA32_STAR 0xC0000081

System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.

Parameters

ECX	MSR_IA32_STAR (0xC0000081)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_STAR);
AsmWriteMsr64 (MSR_IA32_STAR, Msr);

Note: MSR_IA32_STAR is defined as IA32_STAR in SDM.

#define MSR_IA32_SYSENTER_CS 0x00000174

SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.

Parameters

ECX	MSR_IA32_SYSENTER_CS (0x00000174)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_SYSENTER_CS_REGISTER.

Example usage

MSR_IA32_SYSENTER_CS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);
AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);

Note: MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.

#define MSR_IA32_SYSENTER_EIP 0x00000176

SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.

Parameters

ECX	MSR_IA32_SYSENTER_EIP (0x00000176)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);
AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);

Note: MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.

#define MSR_IA32_SYSENTER_ESP 0x00000175

SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.

Parameters

ECX	MSR_IA32_SYSENTER_ESP (0x00000175)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);
AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);

Note: MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.

#define MSR_IA32_THERM_INTERRUPT 0x0000019B

Thermal Interrupt Control (R/W) Enables and disables the generation of an interrupt on temperature transitions detected with the processor's thermal sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.". If CPUID.01H:EDX[22] = 1

Parameters

ECX	MSR_IA32_THERM_INTERRUPT (0x0000019B)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.

Example usage

MSR_IA32_THERM_INTERRUPT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);
AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);

Note: MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.

#define MSR_IA32_THERM_STATUS 0x0000019C

Thermal Status Information (RO) Contains status information about the processor's thermal sensor and automatic thermal monitoring facilities. See Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.

Parameters

ECX	MSR_IA32_THERM_STATUS (0x0000019C)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_THERM_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_THERM_STATUS_REGISTER.

Example usage

MSR_IA32_THERM_STATUS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);

Note: MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.

#define MSR_IA32_THREAD_STALL 0x00000DB2

Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1. Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.

Parameters

ECX	MSR_IA32_THREAD_STALL (0x00000DB2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);

Note: MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.

#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010

See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family / Display Model 05_01H.

Parameters

ECX	MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);

Note: MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.

#define MSR_IA32_TSC_ADJUST 0x0000003B

Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H, ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for a logical processor. Reset value is Zero. A write to IA32_TSC will modify the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does not affect the internal invariant TSC hardware.

Parameters

ECX	MSR_IA32_TSC_ADJUST (0x0000003B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);

Note: MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.

#define MSR_IA32_TSC_AUX 0xC0000103

Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.

Parameters

ECX	MSR_IA32_TSC_AUX (0xC0000103)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_TSC_AUX_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_TSC_AUX_REGISTER.

Example usage

MSR_IA32_TSC_AUX_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);
AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);

Note: MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.

#define MSR_IA32_TSC_DEADLINE 0x000006E0

TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] = 1.

Parameters

ECX	MSR_IA32_TSC_DEADLINE (0x000006E0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);
AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);

Note: MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.

#define MSR_IA32_VMX_BASIC 0x00000480

Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic VMX Information.". If CPUID.01H:ECX.[5] = 1.

Parameters

ECX	MSR_IA32_VMX_BASIC (0x00000480)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

MSR_IA32_VMX_BASIC_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);

Note: MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.

#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00

Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType

#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06

Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType

#define MSR_IA32_VMX_CR0_FIXED0 0x00000486

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7, "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.

Parameters

ECX	MSR_IA32_VMX_CR0_FIXED0 (0x00000486)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);

Note: MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.

#define MSR_IA32_VMX_CR0_FIXED1 0x00000487

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7, "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.

Parameters

ECX	MSR_IA32_VMX_CR0_FIXED1 (0x00000487)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);

Note: MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.

#define MSR_IA32_VMX_CR4_FIXED0 0x00000488

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8, "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.

Parameters

ECX	MSR_IA32_VMX_CR4_FIXED0 (0x00000488)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);

Note: MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.

#define MSR_IA32_VMX_CR4_FIXED1 0x00000489

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8, "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.

Parameters

ECX	MSR_IA32_VMX_CR4_FIXED1 (0x00000489)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);

Note: MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.

#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484

Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5, "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.

Parameters

ECX	MSR_IA32_VMX_ENTRY_CTLS (0x00000484)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);

Note: MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.

#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C

Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10, "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).

Parameters

ECX	MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);

Note: MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.

#define MSR_IA32_VMX_EXIT_CTLS 0x00000483

Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4, "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.

Parameters

ECX	MSR_IA32_VMX_EXIT_CTLS (0x00000483)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);

Note: MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.

#define MSR_IA32_VMX_MISC 0x00000485

Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6, "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.

Parameters

ECX	MSR_IA32_VMX_MISC (0x00000485)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

IA32_VMX_MISC_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);

Note: MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.

#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481

Capability Reporting Register of Pinbased VM-execution Controls (R/O) See Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.

Parameters

ECX	MSR_IA32_VMX_PINBASED_CTLS (0x00000481)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);

Note: MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.

#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482

Capability Reporting Register of Primary Processor-based VM-execution Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution Controls.". If CPUID.01H:ECX.[5] = 1.

Parameters

ECX	MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);

Note: MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.

#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B

Capability Reporting Register of Secondary Processor-based VM-execution Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).

Parameters

ECX	MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);

Note: MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.

#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490

Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).

Parameters

ECX	MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);

Note: MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.

#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F

Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).

Parameters

ECX	MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);

Note: MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.

#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D

Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O) See Appendix A.3.1, "Pin-Based VMExecution Controls.". If ( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).

Parameters

ECX	MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);

Note: MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.

#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E

Capability Reporting Register of Primary Processor-based VM-execution Flex Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).

Parameters

ECX	MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);

Note: MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.

#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A

Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.

Parameters

ECX	MSR_IA32_VMX_VMCS_ENUM (0x0000048A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);

Note: MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.

#define MSR_IA32_VMX_VMFUNC 0x00000491

Capability Reporting Register of VMfunction Controls (R/O). If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).

Parameters

ECX	MSR_IA32_VMX_VMFUNC (0x00000491)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);

Note: MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.

#define MSR_IA32_X2APIC_APICID 0x00000802

x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_APICID (0x00000802)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);

Note: MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.

#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839

x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_CUR_COUNT (0x00000839)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);

Note: MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.

#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E

x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_DIV_CONF (0x0000083E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);
AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);

Note: MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.

#define MSR_IA32_X2APIC_EOI 0x0000080B

x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_EOI (0x0000080B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = 0;
AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);

Note: MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.

#define MSR_IA32_X2APIC_ESR 0x00000828

x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_ESR (0x00000828)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);
AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);

Note: MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.

#define MSR_IA32_X2APIC_ICR 0x00000830

x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_ICR (0x00000830)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);

Note: MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.

#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838

x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_INIT_COUNT (0x00000838)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);
AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);

Note: MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.

#define MSR_IA32_X2APIC_IRR0 0x00000820

x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_IRRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);

Note: MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM. MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM. MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM. MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM. MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM. MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM. MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM. MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.

#define MSR_IA32_X2APIC_IRR1 0x00000821

x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_IRRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);

Note: MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM. MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM. MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM. MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM. MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM. MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM. MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM. MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.

#define MSR_IA32_X2APIC_IRR2 0x00000822

x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_IRRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);

Note: MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM. MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM. MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM. MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM. MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM. MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM. MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM. MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.

#define MSR_IA32_X2APIC_IRR3 0x00000823

x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_IRRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);

Note: MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM. MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM. MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM. MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM. MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM. MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM. MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM. MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.

#define MSR_IA32_X2APIC_IRR4 0x00000824

x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_IRRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);

Note: MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM. MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM. MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM. MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM. MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM. MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM. MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM. MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.

#define MSR_IA32_X2APIC_IRR5 0x00000825

x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_IRRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);

Note: MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM. MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM. MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM. MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM. MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM. MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM. MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM. MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.

#define MSR_IA32_X2APIC_IRR6 0x00000826

x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_IRRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);

Note: MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM. MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM. MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM. MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM. MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM. MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM. MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM. MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.

#define MSR_IA32_X2APIC_IRR7 0x00000827

x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_IRRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);

Note: MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM. MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM. MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM. MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM. MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM. MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM. MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM. MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.

#define MSR_IA32_X2APIC_ISR0 0x00000810

x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_ISRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);

Note: MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM. MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM. MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM. MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM. MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM. MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM. MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM. MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.

#define MSR_IA32_X2APIC_ISR1 0x00000811

x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_ISRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);

Note: MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM. MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM. MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM. MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM. MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM. MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM. MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM. MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.

#define MSR_IA32_X2APIC_ISR2 0x00000812

x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_ISRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);

Note: MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM. MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM. MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM. MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM. MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM. MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM. MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM. MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.

#define MSR_IA32_X2APIC_ISR3 0x00000813

x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_ISRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);

Note: MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM. MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM. MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM. MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM. MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM. MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM. MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM. MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.

#define MSR_IA32_X2APIC_ISR4 0x00000814

x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_ISRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);

Note: MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM. MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM. MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM. MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM. MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM. MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM. MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM. MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.

#define MSR_IA32_X2APIC_ISR5 0x00000815

x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_ISRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);

Note: MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM. MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM. MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM. MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM. MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM. MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM. MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM. MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.

#define MSR_IA32_X2APIC_ISR6 0x00000816

x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_ISRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);

Note: MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM. MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM. MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM. MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM. MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM. MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM. MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM. MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.

#define MSR_IA32_X2APIC_ISR7 0x00000817

x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_ISRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);

Note: MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM. MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM. MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM. MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM. MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM. MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM. MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM. MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.

#define MSR_IA32_X2APIC_LDR 0x0000080D

x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_LDR (0x0000080D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);

Note: MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.

#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F

x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);

Note: MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.

#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837

x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_LVT_ERROR (0x00000837)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);

Note: MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.

#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835

x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);

Note: MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.

#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836

x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);

Note: MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.

#define MSR_IA32_X2APIC_LVT_PMI 0x00000834

x2APIC LVT Performance Monitor Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_LVT_PMI (0x00000834)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);

Note: MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.

#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833

x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);

Note: MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.

#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832

x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_LVT_TIMER (0x00000832)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);

Note: MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.

#define MSR_IA32_X2APIC_PPR 0x0000080A

x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_PPR (0x0000080A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);

Note: MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.

#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F

x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_SELF_IPI (0x0000083F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = 0;
AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);

Note: MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.

#define MSR_IA32_X2APIC_SIVR 0x0000080F

x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_SIVR (0x0000080F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);
AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);

Note: MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.

#define MSR_IA32_X2APIC_TMR0 0x00000818

x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_TMRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);

Note: MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM. MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM. MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM. MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM. MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM. MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM. MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM. MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.

#define MSR_IA32_X2APIC_TMR1 0x00000819

x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_TMRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);

Note: MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM. MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM. MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM. MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM. MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM. MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM. MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM. MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.

#define MSR_IA32_X2APIC_TMR2 0x0000081A

x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_TMRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);

Note: MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM. MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM. MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM. MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM. MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM. MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM. MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM. MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.

#define MSR_IA32_X2APIC_TMR3 0x0000081B

x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_TMRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);

Note: MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM. MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM. MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM. MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM. MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM. MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM. MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM. MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.

#define MSR_IA32_X2APIC_TMR4 0x0000081C

x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_TMRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);

Note: MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM. MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM. MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM. MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM. MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM. MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM. MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM. MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.

#define MSR_IA32_X2APIC_TMR5 0x0000081D

x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_TMRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);

Note: MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM. MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM. MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM. MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM. MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM. MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM. MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM. MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.

#define MSR_IA32_X2APIC_TMR6 0x0000081E

x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_TMRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);

Note: MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM. MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM. MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM. MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM. MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM. MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM. MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM. MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.

#define MSR_IA32_X2APIC_TMR7 0x0000081F

x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_TMRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);

Note: MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM. MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM. MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM. MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM. MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM. MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM. MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM. MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.

#define MSR_IA32_X2APIC_TPR 0x00000808

x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_TPR (0x00000808)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);
AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);

Note: MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.

#define MSR_IA32_X2APIC_VERSION 0x00000803

x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.

Parameters

ECX	MSR_IA32_X2APIC_VERSION (0x00000803)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);

Note: MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.

#define MSR_IA32_XSS 0x00000DA0

Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.

Parameters

ECX	MSR_IA32_XSS (0x00000DA0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IA32_XSS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IA32_XSS_REGISTER.

Example usage

MSR_IA32_XSS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);
AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);

Note: MSR_IA32_XSS is defined as IA32_XSS in SDM.

#define STM_FEATURES_IA32E 0x1

Define values for the MonitorFeatures field of MSEG_HEADER

Enumeration Type Documentation

enum RTIT_TOPA_MEMORY_SIZE

The size of the associated output region usd by Topa.

Enumerator
RtitTopaMemorySize4K
RtitTopaMemorySize8K
RtitTopaMemorySize16K
RtitTopaMemorySize32K
RtitTopaMemorySize64K
RtitTopaMemorySize128K
RtitTopaMemorySize256K
RtitTopaMemorySize512K
RtitTopaMemorySize1M
RtitTopaMemorySize2M
RtitTopaMemorySize4M
RtitTopaMemorySize8M
RtitTopaMemorySize16M
RtitTopaMemorySize32M
RtitTopaMemorySize64M
RtitTopaMemorySize128M

Data Structures

Macros

Enumerations

Detailed Description

Macro Definition Documentation

Enumeration Type Documentation