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MdePkg[all]
1.08
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MdePkg[all]
1.08
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MSR information returned for MSR index #IA32_VMX_MISC
| struct { ... } IA32_VMX_MISC_REGISTER::Bits |
Individual bit fields
| UINT32 IA32_VMX_MISC_REGISTER::BlockSmiSupported |
[Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1 (see Section 34.14.4).
| UINT32 IA32_VMX_MISC_REGISTER::HltActivityStateSupported |
[Bit 6] reports (if set) the support for activity state 1 (HLT).
| UINT32 IA32_VMX_MISC_REGISTER::MsegRevisionIdentifier |
[Bits 63:32] Reports the 32-bit MSEG revision identifier used by the processor.
| UINT32 IA32_VMX_MISC_REGISTER::MsrStoreListMaximum |
[Bit 27:25] Bits 27:25 is used to compute the recommended maximum number of MSRs that should appear in the VM-exit MSR-store list, the VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the recommended maximum number of MSRs to be included in each list. If the limit is exceeded, undefined processor behavior may result (including a machine check during the VMX transition).
| UINT32 IA32_VMX_MISC_REGISTER::NumberOfCr3TargetValues |
[Bits 24:16] Indicate the number of CR3-target values supported by the processor. This number is a value between 0 and 256, inclusive (bit 24 is set if and only if bits 23:16 are clear).
| UINT32 IA32_VMX_MISC_REGISTER::ProcessorTraceSupported |
[Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used in VMX operation. If the processor supports Intel PT but does not allow it to be used in VMX operation, execution of VMXON clears IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30); any attempt to set that bit while in VMX operation (including VMX root operation) using the WRMSR instruction causes a general-protection exception.
| UINT32 IA32_VMX_MISC_REGISTER::Reserved1 |
| UINT32 IA32_VMX_MISC_REGISTER::Reserved2 |
| UINT32 IA32_VMX_MISC_REGISTER::ShutdownActivityStateSupported |
[Bit 7] reports (if set) the support for activity state 2 (shutdown).
| UINT32 IA32_VMX_MISC_REGISTER::SmBaseMsrSupported |
[Bit 15] If read as 1, the RDMSR instruction can be used in system- management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH). See Section 34.15.6.3.
| UINT64 IA32_VMX_MISC_REGISTER::Uint64 |
All bit fields as a 64-bit value
| UINT32 IA32_VMX_MISC_REGISTER::VmExitEferLma |
[Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more details. This bit is read as 1 on any logical processor that supports the 1-setting of the "unrestricted guest" VM-execution control.
| UINT32 IA32_VMX_MISC_REGISTER::VmInjectSupported |
[Bit 30] If read as 1, VM entry allows injection of a software interrupt, software exception, or privileged software exception with an instruction length of 0.
| UINT32 IA32_VMX_MISC_REGISTER::VmWriteSupported |
[Bit 29] read as 1, software can use VMWRITE to write to any supported field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit information fields.
| UINT32 IA32_VMX_MISC_REGISTER::VmxTimerRatio |
[Bits 4:0] Reports a value X that specifies the relationship between the rate of the VMX-preemption timer and that of the timestamp counter (TSC). Specifically, the VMX-preemption timer (if it is active) counts down by 1 every time bit X in the TSC changes due to a TSC increment.
| UINT32 IA32_VMX_MISC_REGISTER::WaitForSipiActivityStateSupported |
[Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).
1.8.6 
