MSEG_HEADER Struct Reference

Data Fields
UINT32	MsegHeaderRevision
UINT32	MonitorFeatures
UINT32	GdtrLimit
UINT32	GdtrBaseOffset
UINT32	CsSelector
UINT32	EipOffset
UINT32	EspOffset
UINT32	Cr3Offset
UINT8	Reserved [SIZE_2KB-8 *sizeof(UINT32)]

Detailed Description

MSEG header that is located at the physical address specified by the MsegBase field of MSR_IA32_SMM_MONITOR_CTL_REGISTER.

Field Documentation

UINT32 MSEG_HEADER::Cr3Offset

UINT32 MSEG_HEADER::CsSelector

UINT32 MSEG_HEADER::EipOffset

UINT32 MSEG_HEADER::EspOffset

UINT32 MSEG_HEADER::GdtrBaseOffset

UINT32 MSEG_HEADER::GdtrLimit

UINT32 MSEG_HEADER::MonitorFeatures

Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field is the IA-32e mode SMM feature bit. It indicates whether the logical processor will be in IA-32e mode after the STM is activated.

UINT32 MSEG_HEADER::MsegHeaderRevision

Different processors may use different MSEG revision identifiers. These identifiers enable software to avoid using an MSEG header formatted for one processor on a processor that uses a different format. Software can discover the MSEG revision identifier that a processor uses by reading the VMX capability MSR IA32_VMX_MISC.

UINT8 MSEG_HEADER::Reserved[SIZE_2KB-8 *sizeof(UINT32)]

Pad header so total size is 2KB