MSR information returned for MSR index MSR_IA32_L3_QOS_CFG
struct { ... } MSR_IA32_L3_QOS_CFG_REGISTER::Bits |
UINT32 MSR_IA32_L3_QOS_CFG_REGISTER::Enable |
[Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate in Code and Data Prioritization (CDP) mode.
UINT32 MSR_IA32_L3_QOS_CFG_REGISTER::Reserved1 |
UINT32 MSR_IA32_L3_QOS_CFG_REGISTER::Reserved2 |
UINT32 MSR_IA32_L3_QOS_CFG_REGISTER::Uint32 |
All bit fields as a 32-bit value
UINT64 MSR_IA32_L3_QOS_CFG_REGISTER::Uint64 |
All bit fields as a 64-bit value