MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Union Reference

Data Fields
struct {
UINT32   Ovf_PMCn:32
UINT32   Ovf_FIXED_CTRn:23
UINT32   Trace_ToPA_PMI:1
UINT32   Reserved2:5
UINT32   Ovf_Uncore:1
UINT32   OvfBuf:1
UINT32   CondChgd:1
}	Bits
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_IA32_PERF_GLOBAL_OVF_CTRL

Field Documentation

struct { ... } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::CondChgd

[Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.

UINT32 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_FIXED_CTRn

[Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. If CPUID.0AH: EDX[4:0] > n. Clear bitmask. Only the first n-1 bits are valid. Bits 22:n are reserved.

UINT32 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_PMCn

[Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. Clear bitmask. Only the first n-1 bits are valid. Bits 31:n are reserved.

UINT32 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_Uncore

[Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / Display Model 06_2EH.

UINT32 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::OvfBuf

[Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.

UINT32 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Reserved2

UINT32 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Trace_ToPA_PMI

[Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.

UINT64 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value