MSR_IA32_L2_QOS_CFG_REGISTER Union Reference

Data Fields
struct {
UINT32   Enable:1
UINT32   Reserved1:31
UINT32   Reserved2:32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_IA32_L2_QOS_CFG

Field Documentation

struct { ... } MSR_IA32_L2_QOS_CFG_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_L2_QOS_CFG_REGISTER::Enable

[Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate in Code and Data Prioritization (CDP) mode.

UINT32 MSR_IA32_L2_QOS_CFG_REGISTER::Reserved1

UINT32 MSR_IA32_L2_QOS_CFG_REGISTER::Reserved2

UINT32 MSR_IA32_L2_QOS_CFG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_L2_QOS_CFG_REGISTER::Uint64

All bit fields as a 64-bit value