MSR_IA32_MTRR_PHYSMASK_REGISTER Union Reference

Data Fields
struct {
UINT32   Reserved1:11
UINT32   V:1
UINT32   PhysMask:20
UINT32   PhysMaskHi:32
}	Bits
UINT64	Uint64

Detailed Description

MSR information returned for MSR indexes MSR_IA32_MTRR_PHYSMASK0 to MSR_IA32_MTRR_PHYSMASK9

Field Documentation

struct { ... } MSR_IA32_MTRR_PHYSMASK_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_MTRR_PHYSMASK_REGISTER::PhysMask

[Bits 31:12] PhysMask. MTRR address range mask.

UINT32 MSR_IA32_MTRR_PHYSMASK_REGISTER::PhysMaskHi

[Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask. MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the maximum physical address range supported by the processor. It is reported by CPUID leaf function 80000008H. If CPUID does not support leaf 80000008H, the processor supports 36-bit physical address size, then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.

UINT32 MSR_IA32_MTRR_PHYSMASK_REGISTER::Reserved1

UINT64 MSR_IA32_MTRR_PHYSMASK_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_IA32_MTRR_PHYSMASK_REGISTER::V

[Bit 11] Valid Enable range mask.