Detailed Description

MSR information returned for MSR index MSR_IA32_PERF_GLOBAL_STATUS_RESET

Field Documentation

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::ASCI

[Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.

struct { ... } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CondChgd

[Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CTR_Frz

[Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::LBR_Frz

[Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_FIXED_CTRn

[Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. If CPUID.0AH: EDX[4:0] > n. Clear bitmask. Only the first n-1 bits are valid. Bits 22:n are reserved.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMCn

[Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. Clear bitmask. Only the first n-1 bits are valid. Bits 31:n are reserved.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_Uncore

[Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / Display Model 06_2EH.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::OvfBuf

[Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Reserved2

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Trace_ToPA_PMI

[Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.

UINT64 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Uint64

All bit fields as a 64-bit value