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Data Structures | Macros
XeonDMsr.h File Reference

Data Structures

union  MSR_XEON_D_PPIN_CTL_REGISTER
 
union  MSR_XEON_D_PLATFORM_INFO_REGISTER
 
union  MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
 
union  MSR_XEON_D_IA32_MCG_CAP_REGISTER
 
union  MSR_XEON_D_SMM_MCA_CAP_REGISTER
 
union  MSR_XEON_D_TEMPERATURE_TARGET_REGISTER
 
union  MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
 
union  MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
 
union  MSR_XEON_D_RAPL_POWER_UNIT_REGISTER
 
union  MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER
 
union  MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER
 
union  MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
 
union  MSR_XEON_D_IA32_QM_EVTSEL_REGISTER
 
union  MSR_XEON_D_IA32_PQR_ASSOC_REGISTER
 
union  MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER
 
union  MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER
 
union  MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER
 

Macros

#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel)
 
#define MSR_XEON_D_PPIN_CTL   0x0000004E
 
#define MSR_XEON_D_PPIN   0x0000004F
 
#define MSR_XEON_D_PLATFORM_INFO   0x000000CE
 
#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL   0x000000E2
 
#define MSR_XEON_D_IA32_MCG_CAP   0x00000179
 
#define MSR_XEON_D_SMM_MCA_CAP   0x0000017D
 
#define MSR_XEON_D_TEMPERATURE_TARGET   0x000001A2
 
#define MSR_XEON_D_TURBO_RATIO_LIMIT   0x000001AD
 
#define MSR_XEON_D_TURBO_RATIO_LIMIT1   0x000001AE
 
#define MSR_XEON_D_RAPL_POWER_UNIT   0x00000606
 
#define MSR_XEON_D_DRAM_POWER_LIMIT   0x00000618
 
#define MSR_XEON_D_DRAM_ENERGY_STATUS   0x00000619
 
#define MSR_XEON_D_DRAM_PERF_STATUS   0x0000061B
 
#define MSR_XEON_D_DRAM_POWER_INFO   0x0000061C
 
#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT   0x00000620
 
#define MSR_XEON_D_PP0_ENERGY_STATUS   0x00000639
 
#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS   0x00000690
 
#define MSR_XEON_D_IA32_QM_EVTSEL   0x00000C8D
 
#define MSR_XEON_D_IA32_PQR_ASSOC   0x00000C8F
 
#define MSR_XEON_D_TURBO_RATIO_LIMIT3   0x000001AC
 
#define MSR_XEON_D_IA32_L3_QOS_CFG   0x00000C81
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_0   0x00000C90
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_1   0x00000C91
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_2   0x00000C92
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_3   0x00000C93
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_4   0x00000C94
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_5   0x00000C95
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_6   0x00000C96
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_7   0x00000C97
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_8   0x00000C98
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_9   0x00000C99
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_10   0x00000C9A
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_11   0x00000C9B
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_12   0x00000C9C
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_13   0x00000C9D
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_14   0x00000C9E
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_15   0x00000C9F
 

Detailed Description

MSR Definitions for Intel(R) Xeon(R) Processor D product Family.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_XEON_D_PROCESSOR (   DisplayFamily,
  DisplayModel 
)
Value:
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x4F || \
DisplayModel == 0x56 \
) \
)

Is Intel(R) Xeon(R) Processor D product Family?

Parameters
DisplayFamilyDisplay Family ID
DisplayModelDisplay Model ID
Return values
TRUEYes, it is.
FALSENo, it isn't.
#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS   0x00000690

Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency refers to processor core frequency).

Parameters
ECXMSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.

Example usage

MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);
AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
Note
MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
#define MSR_XEON_D_DRAM_ENERGY_STATUS   0x00000619

Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.

Parameters
ECXMSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.

Example usage

MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);
Note
MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
#define MSR_XEON_D_DRAM_PERF_STATUS   0x0000061B

Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters
ECXMSR_XEON_D_DRAM_PERF_STATUS (0x0000061B)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);
Note
MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
#define MSR_XEON_D_DRAM_POWER_INFO   0x0000061C

Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters
ECXMSR_XEON_D_DRAM_POWER_INFO (0x0000061C)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);
AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);
Note
MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
#define MSR_XEON_D_DRAM_POWER_LIMIT   0x00000618

Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters
ECXMSR_XEON_D_DRAM_POWER_LIMIT (0x00000618)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);
AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);
Note
MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
#define MSR_XEON_D_IA32_L3_QOS_CFG   0x00000C81

Package. Cache Allocation Technology Configuration (R/W).

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_0   0x00000C90

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_1   0x00000C91

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_10   0x00000C9A

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_11   0x00000C9B

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_12   0x00000C9C

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_13   0x00000C9D

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_14   0x00000C9E

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_15   0x00000C9F

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_2   0x00000C92

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_3   0x00000C93

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_4   0x00000C94

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_5   0x00000C95

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_6   0x00000C96

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_7   0x00000C97

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_8   0x00000C98

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_L3_QOS_MASK_9   0x00000C99

Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >= n.

Parameters
ECXMSR_XEON_D_IA32_L3_QOS_MASK_n
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.

Example usage

MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
Note
MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
#define MSR_XEON_D_IA32_MCG_CAP   0x00000179

Thread. Global Machine Check Capability (R/O).

Parameters
ECXMSR_XEON_D_IA32_MCG_CAP (0x00000179)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.

Example usage

MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);
Note
MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
#define MSR_XEON_D_IA32_PQR_ASSOC   0x00000C8F

THREAD. Resource Association Register (R/W).

Parameters
ECXMSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.

Example usage

MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);
AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);
Note
MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
#define MSR_XEON_D_IA32_QM_EVTSEL   0x00000C8D

THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.

Parameters
ECXMSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.

Example usage

MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);
AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);
Note
MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT   0x00000620

Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select.

Parameters
ECXMSR_XEON_D_MSRUNCORE_RATIO_LIMIT (0x00000620)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.

Example usage

MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT);
AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL   0x000000E2

Core. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. <http://biosbits.org>__.

Parameters
ECXMSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.

Example usage

MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
Note
MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
#define MSR_XEON_D_PLATFORM_INFO   0x000000CE

Package. See http://biosbits.org.

Parameters
ECXMSR_XEON_D_PLATFORM_INFO (0x000000CE)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.

Example usage

MSR_XEON_D_PLATFORM_INFO_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);
AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);
Note
MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
#define MSR_XEON_D_PP0_ENERGY_STATUS   0x00000639

Package. Reserved (R/O) Reads return 0.

Parameters
ECXMSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS);
Note
MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
#define MSR_XEON_D_PPIN   0x0000004F

Package. Protected Processor Inventory Number (R/O). Protected Processor Inventory Number (R/O) See Table 2-25.

Parameters
ECXMSR_XEON_D_PPIN (0x0000004F)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);
Note
MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM.
#define MSR_XEON_D_PPIN_CTL   0x0000004E

Package. Protected Processor Inventory Number Enable Control (R/W).

Parameters
ECXMSR_XEON_D_PPIN_CTL (0x0000004E)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.

Example usage

MSR_XEON_D_PPIN_CTL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);
AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);
Note
MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
#define MSR_XEON_D_RAPL_POWER_UNIT   0x00000606

Package. Unit Multipliers used in RAPL Interfaces (R/O).

Parameters
ECXMSR_XEON_D_RAPL_POWER_UNIT (0x00000606)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.

Example usage

MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);
Note
MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
#define MSR_XEON_D_SMM_MCA_CAP   0x0000017D

THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM.

Parameters
ECXMSR_XEON_D_SMM_MCA_CAP (0x0000017D)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.

Example usage

MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);
AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);
Note
MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
#define MSR_XEON_D_TEMPERATURE_TARGET   0x000001A2

Package.

Parameters
ECXMSR_XEON_D_TEMPERATURE_TARGET (0x000001A2)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.

Example usage

MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);
AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);
Note
MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
#define MSR_XEON_D_TURBO_RATIO_LIMIT   0x000001AD

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters
ECXMSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.

Example usage

MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);
Note
MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
#define MSR_XEON_D_TURBO_RATIO_LIMIT1   0x000001AE

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters
ECXMSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.

Example usage

MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);
Note
MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
#define MSR_XEON_D_TURBO_RATIO_LIMIT3   0x000001AC

Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters
ECXMSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC)
EAXLower 32-bits of MSR value. Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.

Example usage

MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);
Note
MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM.