MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Union Reference

Data Fields
struct {
UINT32   EventID:8
UINT32   Reserved1:24
UINT32   RMID:10
UINT32   Reserved2:22
}	Bits
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_D_IA32_QM_EVTSEL

Field Documentation

struct { ... } MSR_XEON_D_IA32_QM_EVTSEL_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER::EventID

[Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3 occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03: Local memory bandwidth monitoring All other encoding reserved.

UINT32 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER::Reserved1

UINT32 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER::Reserved2

UINT32 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER::RMID

[Bits 41:32] RMID (RW).

UINT64 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER::Uint64

All bit fields as a 64-bit value