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MdePkg[all]
1.08
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MdePkg[all]
1.08
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MSR Definitions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
| #define IS_SKYLAKE_PROCESSOR | ( | DisplayFamily, | |
| DisplayModel | |||
| ) |
Is Intel processors based on the Skylake microarchitecture?
| DisplayFamily | Display Family ID |
| DisplayModel | Display Model ID |
| TRUE | Yes, it is. |
| FALSE | No, it isn't. |
| #define MSR_SKYLAKE_ANY_CORE_C0 0x00000659 |
Package. Any Core C0 Residency. (R/O). Increment at the same rate as the TSC. The increment each cycle is one if any processor core in the package is in C0.
| ECX | MSR_SKYLAKE_ANY_CORE_C0 (0x00000659) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A |
Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate as the TSC. The increment each cycle is one if any processor graphic device's compute engines are in C0.
| ECX | MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350 |
Branch Monitoring Global Control (R/W).
| ECX | MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER. |
Example usage
| #define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351 |
Branch Monitoring Global Status (R/W).
| ECX | MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER. |
Example usage
| #define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660 |
Core. Core C1 Residency Counter (R/O). Value since last reset for the Core C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC). This counter counts in case both of the core's threads are in an idle state and at least one of the core's thread residency is in a C1 state or in one of its sub states. The counter is updated only after a core C state exit. Note: Always reads 0 if core C1 is unsupported. A value of zero indicates that this processor does not support core C1 or never entered core C1 level state.
| ECX | MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662 |
Core. Core C3 Residency Counter (R/O). Will always return 0.
| ECX | MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B |
Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment at the same rate as the TSC. The increment each cycle is one if at least one compute engine of the processor graphics is in C0 and at least one processor core in the package is also in C0.
| ECX | MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653 |
Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.
| ECX | MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F |
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency refers to processor core frequency).
| ECX | MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER. |
Example usage
| #define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619 |
Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.
| ECX | MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER. |
Example usage
| #define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B |
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
| ECX | MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C |
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
| ECX | MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618 |
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
| ECX | MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0 |
Package. Indicator of Frequency Clipping in the Processor Graphics (R/W) (frequency refers to processor graphics frequency).
| ECX | MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. |
Example usage
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90 |
Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0.
| ECX | MSR_SKYLAKE_IA32_L3_QOS_MASK_N |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER. |
Example usage
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91 |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92 |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93 |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94 |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95 |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96 |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97 |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98 |
| #define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99 |
| #define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179 |
Thread. Global Machine Check Capability (R/O).
| ECX | MSR_SKYLAKE_IA32_MCG_CAP (0x00000179) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER. |
Example usage
| #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E |
See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring Version 4.".
| ECX | MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. |
Example usage
| #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390 |
See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring Version 4.".
| ECX | MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. |
Example usage
| #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391 |
See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring Version 4.".
| ECX | MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. |
Example usage
| #define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F |
THREAD. Resource Association Register (R/W).
| ECX | MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER. |
Example usage
| #define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D |
THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.
| ECX | MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690 |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0 |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691 |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1 |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692 |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2 |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693 |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3 |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694 |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4 |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695 |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5 |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696 |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6 |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697 |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7 |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698 |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8 |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699 |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9 |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F |
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF |
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.10.
| ECX | MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9 |
Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that points to the MSR containing the most recent branch record.
| ECX | MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9 |
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR Stack.".
| ECX | MSR_SKYLAKE_LBR_INFO_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620 |
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select.
| ECX | MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER. |
Example usage
| #define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7 |
Thread. FrontEnd Precise Event Condition Select (R/W).
| ECX | MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER. |
Example usage
| #define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8 |
Package. Package C3 Residency Counter (R/O). Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states.
| ECX | MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2 |
Core. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. <http://biosbits.org/>__.
| ECX | MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER. |
Example usage
| #define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652 |
Package. HDC Configuration (R/W)..
| ECX | MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER. |
Example usage
| #define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656 |
Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.
| ECX | MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655 |
Package. Accumulate the cycles the package was in C2 state and at least one logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.
| ECX | MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D |
Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both platform vendor hardware implementation and BIOS enablement support it. This MSR will read 0 if not valid.
| ECX | MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER. |
Example usage
| #define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE |
Package. Platform Information Contains power management and other model specific features enumeration. See http://biosbits.org.
| ECX | MSR_SKYLAKE_PLATFORM_INFO (0x000000CE) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER. |
Example usage
| #define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C |
Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to limit power consumption of the platform devices to the specified values. The Long Duration power consumption is specified via Platform_Power_Limit_1 and Platform_Power_Limit_1_Time. The Short Duration power consumption limit is specified via the Platform_Power_Limit_2 with duration chosen by the processor. The processor implements an exponential-weighted algorithm in the placement of the time windows.
| ECX | MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER. |
Example usage
| #define MSR_SKYLAKE_POWER_CTL 0x000001FC |
Core. Power Control Register See http://biosbits.org.
| ECX | MSR_SKYLAKE_POWER_CTL (0x000001FC) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER. |
Example usage
| #define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639 |
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".
| ECX | MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
Package. Reserved (R/O) Reads return 0.
| ECX | MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639 |
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".
| ECX | MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
Package. Reserved (R/O) Reads return 0.
| ECX | MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_PPERF 0x0000064E |
Thread. Productive Performance Count. (R/O). Hardware's view of workload scalability. See Section 14.4.5.1.
| ECX | MSR_SKYLAKE_PPERF (0x0000064E) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_PPIN 0x0000004F |
Package. Protected Processor Inventory Number (R/O). Protected Processor Inventory Number (R/O) See Table 2-25.
| ECX | MSR_SKYLAKE_PPIN (0x0000004F) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_PPIN_CTL 0x0000004E |
Package. Protected Processor Inventory Number Enable Control (R/W).
| ECX | MSR_SKYLAKE_PPIN_CTL (0x0000004E) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER. |
Example usage
| #define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4 |
Core. Processor Reserved Memory Range Register - Physical Base Control Register (R/W).
| ECX | MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER. |
Example usage
| #define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5 |
Core. Processor Reserved Memory Range Register - Physical Mask Control Register (R/W).
| ECX | MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER. |
Example usage
| #define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB |
Core. Valid PRMRR Configurations (R/W).
| ECX | MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER. |
Example usage
| #define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606 |
Package. Unit Multipliers Used in RAPL Interfaces (R/O).
| ECX | MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER. |
Example usage
| #define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1 |
Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W) (frequency refers to ring interconnect in the uncore).
| ECX | MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER. |
Example usage
| #define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620 |
Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits for the LLC and Ring.
| ECX | MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER. |
Example usage
| #define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0 |
| #define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1 |
| #define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300 |
Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package. Lower 64 bits of an 128-bit external entropy value for key derivation of an enclave.
| ECX | MSR_SKYLAKE_SGXOWNEREPOCH0 (0x00000300) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301 |
Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package. Upper 64 bits of an 128-bit external entropy value for key derivation of an enclave.
| ECX | MSR_SKYLAKE_SGXOWNEREPOCH1 (0x00000301) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D |
THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM.
| ECX | MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER. |
Example usage
| #define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2 |
Package. Temperature Target.
| ECX | MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER. |
Example usage
| #define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080 |
Package. NPK Address Used by AET Messages (R/W).
| ECX | MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER. |
Example usage
| #define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD |
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.
| ECX | MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. |
Example usage
| #define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE |
Package. This register defines the active core ranges for each frequency point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored. The last valid entry must have NUMCORE >= the number of cores in the SKU. If any of the rules above are broken, the configuration is silently rejected.
| ECX | MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER. |
Example usage
| #define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0 |
Package. Uncore Arb unit, performance counter 0.
| ECX | MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1 |
Package. Uncore Arb unit, performance counter 1.
| ECX | MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2 |
Package. Uncore Arb unit, counter 0 event select MSR.
| ECX | MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3 |
Package. Uncore Arb unit, counter 1 event select MSR.
| ECX | MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706 |
Package. Uncore C-Box 0, performance counter 0.
| ECX | MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707 |
Package. Uncore C-Box 0, performance counter 1.
| ECX | MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700 |
Package. Uncore C-Box 0, counter 0 event select MSR.
| ECX | MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701 |
Package. Uncore C-Box 0, counter 1 event select MSR.
| ECX | MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716 |
Package. Uncore C-Box 1, performance counter 0.
| ECX | MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717 |
Package. Uncore C-Box 1, performance counter 1.
| ECX | MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710 |
Package. Uncore C-Box 1, counter 0 event select MSR.
| ECX | MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711 |
Package. Uncore C-Box 1, counter 1 event select MSR.
| ECX | MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726 |
Package. Uncore C-Box 2, performance counter 0.
| ECX | MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727 |
Package. Uncore C-Box 2, performance counter 1.
| ECX | MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720 |
Package. Uncore C-Box 2, counter 0 event select MSR.
| ECX | MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721 |
Package. Uncore C-Box 2, counter 1 event select MSR.
| ECX | MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736 |
Package. Uncore C-Box 3, performance counter 0.
| ECX | MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737 |
Package. Uncore C-Box 3, performance counter 1.
| ECX | MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730 |
Package. Uncore C-Box 3, counter 0 event select MSR.
| ECX | MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731 |
Package. Uncore C-Box 3, counter 1 event select MSR.
| ECX | MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396 |
Package. Uncore C-Box configuration information (R/O).
| ECX | MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER. |
Example usage
| #define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395 |
Package. Uncore fixed counter.
| ECX | MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER. |
Example usage
| #define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394 |
Package. Uncore fixed counter control (R/W).
| ECX | MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER. |
Example usage
| #define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01 |
Package. Uncore PMU global control.
| ECX | MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER. |
Example usage
| #define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02 |
Package. Uncore PMU main status.
| ECX | MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER. |
Example usage
| #define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4 |
Package. (R/W) The PRMRR range is used to protect Xucode memory from unauthorized reads and writes. Any IO access to this range is aborted. This register controls the location of the PRMRR range by indicating its starting address. It functions in tandem with the PRMRR mask register.
| ECX | MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER. |
Example usage
| #define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5 |
Package. (R/W) This register controls the size of the PRMRR range by indicating which address bits must match the PRMRR base register value.
| ECX | MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER. |
Example usage
| #define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658 |
Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate as the TSC. The increment each cycle is weighted by the number of processor cores in the package that reside in C0. If N cores are simultaneously in C0, then each cycle the counter increments by N.
| ECX | MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
1.8.6 
