MSR information returned for MSR index MSR_SKYLAKE_RING_PERF_LIMIT_REASONS
struct { ... } MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::Bits |
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::OtherLog |
[Bit 24] Other Log When set, indicates that the OTHER Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::OtherStatus |
[Bit 8] Other Status (R0) When set, frequency is reduced due to electrical or other constraints.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::PL1Log |
[Bit 26] Package/Platform-Level PL1 Power Limiting Log When set, indicates that the Package/Platform Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::PL1Status |
[Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When set, frequency is reduced due to package/Platform-level power limiting PL1.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::PL2Log |
[Bit 27] Package/Platform-Level PL2 Power Limiting Log When set, indicates that the Package/Platform Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::PL2Status |
[Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When set, frequency is reduced due to package/Platform-level power limiting PL2/PL3.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Log |
[Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Status |
[Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to assertion of external PROCHOT.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::Reserved1 |
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::Reserved2 |
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::Reserved3 |
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::Reserved4 |
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::Reserved5 |
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::Reserved6 |
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::Reserved7 |
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::RunningAverageThermalLimitLog |
[Bit 21] Running Average Thermal Limit Log When set, indicates that the RATL Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::RunningAverageThermalLimitStatus |
[Bit 5] Running Average Thermal Limit Status (R0) When set, frequency is reduced due to running average thermal limit.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::ThermalLog |
[Bit 17] Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::ThermalStatus |
[Bit 1] Thermal Status (R0) When set, frequency is reduced due to a thermal event.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::Uint32 |
All bit fields as a 32-bit value
UINT64 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::Uint64 |
All bit fields as a 64-bit value
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::VRThermalDesignCurrentLog |
[Bit 23] VR Thermal Design Current Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::VRThermalDesignCurrentStatus |
[Bit 7] VR Thermal Design Current Status (R0) When set, frequency is reduced due to VR TDC limit.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::VRThermAlertLog |
[Bit 22] VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::VRThermAlertStatus |
[Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due to a thermal alert from a processor Voltage Regulator.