MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Union Reference

Data Fields
struct {
UINT32   Ovf_PMC0:1
UINT32   Ovf_PMC1:1
UINT32   Ovf_PMC2:1
UINT32   Ovf_PMC3:1
UINT32   Ovf_PMC4:1
UINT32   Ovf_PMC5:1
UINT32   Ovf_PMC6:1
UINT32   Ovf_PMC7:1
UINT32   Reserved1:24
UINT32   Ovf_FixedCtr0:1
UINT32   Ovf_FixedCtr1:1
UINT32   Ovf_FixedCtr2:1
UINT32   Reserved2:20
UINT32   Trace_ToPA_PMI:1
UINT32   Reserved3:2
UINT32   LBR_Frz:1
UINT32   CTR_Frz:1
UINT32   ASCI:1
UINT32   Ovf_Uncore:1
UINT32   Ovf_BufDSSAVE:1
UINT32   Reserved4:1
}	Bits
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET

Field Documentation

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::ASCI

[Bit 60] Thread. Set 1 to cause ASCI = 1.

struct { ... } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::CTR_Frz

[Bit 59] Thread. Set 1 to cause CTR_Frz = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::LBR_Frz

[Bit 58] Thread. Set 1 to cause LBR_Frz = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_BufDSSAVE

[Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_FixedCtr0

[Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_FixedCtr1

[Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_FixedCtr2

[Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC0

[Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC1

[Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC2

[Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC3

[Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC4

[Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC5

[Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC6

[Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC7

[Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_Uncore

[Bit 61] Thread. Set 1 to cause Ovf_Uncore.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Reserved1

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Reserved2

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Reserved3

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Reserved4

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Trace_ToPA_PMI

[Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.

UINT64 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Uint64

All bit fields as a 64-bit value