MSR_SKYLAKE_POWER_CTL_REGISTER Union Reference

Data Fields
struct {
UINT32   Reserved1:1
UINT32   C1EEnable:1
UINT32   Reserved2:17
UINT32   Fix_Me_1:1
UINT32   DisableEnergyEfficiencyOptimization:1
UINT32   Reserved3:11
UINT32   Reserved4:32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SKYLAKE_POWER_CTL

Field Documentation

struct { ... } MSR_SKYLAKE_POWER_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_POWER_CTL_REGISTER::C1EEnable

[Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep Technology operating point when all execution cores enter MWAIT (C1).

UINT32 MSR_SKYLAKE_POWER_CTL_REGISTER::DisableEnergyEfficiencyOptimization

[Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit disables the P-States energy efficiency optimization. Default value is 0. Disable/enable the energy efficiency optimization in P-State legacy mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS desired or OS maximize to the OS minimize performance setting.

UINT32 MSR_SKYLAKE_POWER_CTL_REGISTER::Fix_Me_1

[Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit disables the Race to Halt optimization and avoids this optimization limitation to execute below the most efficient frequency ratio. Default value is 0 for processors that support Race to Halt optimization. Default value is 1 for processors that do not support Race to Halt optimization.

UINT32 MSR_SKYLAKE_POWER_CTL_REGISTER::Reserved1

UINT32 MSR_SKYLAKE_POWER_CTL_REGISTER::Reserved2

UINT32 MSR_SKYLAKE_POWER_CTL_REGISTER::Reserved3

UINT32 MSR_SKYLAKE_POWER_CTL_REGISTER::Reserved4

UINT32 MSR_SKYLAKE_POWER_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_POWER_CTL_REGISTER::Uint64

All bit fields as a 64-bit value