Data Structures
union	MSR_XEON_PHI_SMI_COUNT_REGISTER

union	MSR_XEON_PHI_PPIN_CTL_REGISTER

union	MSR_XEON_PHI_PLATFORM_INFO_REGISTER

union	MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER

union	MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER

union	MSR_XEON_PHI_FEATURE_CONFIG_REGISTER

union	MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER

union	MSR_XEON_PHI_SMM_MCA_CAP_REGISTER

union	MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER

union	MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER

union	MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER

union	MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER

union	MSR_XEON_PHI_LBR_SELECT_REGISTER

union	MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER

union	MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER

union	MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER

Macros
#define	IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel)

#define	MSR_XEON_PHI_SMI_COUNT 0x00000034

#define	MSR_XEON_PHI_PPIN_CTL 0x0000004E

#define	MSR_XEON_PHI_PPIN 0x0000004F

#define	MSR_XEON_PHI_PLATFORM_INFO 0x000000CE

#define	MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2

#define	MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4

#define	MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C

#define	MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140

#define	MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D

#define	MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0

#define	MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2

#define	MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4

#define	MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6

#define	MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7

#define	MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD

#define	MSR_XEON_PHI_LBR_SELECT 0x000001C8

#define	MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9

#define	MSR_XEON_PHI_LER_FROM_LIP 0x000001DD

#define	MSR_XEON_PHI_LER_TO_LIP 0x000001DE

#define	MSR_XEON_PHI_PEBS_ENABLE 0x000003F1

#define	MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8

#define	MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9

#define	MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA

#define	MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC

#define	MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD

#define	MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF

#define	MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C

#define	MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491

#define	MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606

#define	MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D

#define	MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610

#define	MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611

#define	MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613

#define	MSR_XEON_PHI_PKG_POWER_INFO 0x00000614

#define	MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618

#define	MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619

#define	MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B

#define	MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C

#define	MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620

#define	MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638

#define	MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639

#define	MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648

#define	MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649

#define	MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A

#define	MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B

#define	MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C

#define	MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690

Detailed Description

MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_XEON_PHI_PROCESSOR	(	DisplayFamily,
		DisplayModel
	)

Value:

(DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x57 || \
    DisplayModel == 0x85    \
    )                       \
   )

Is Intel(R) Xeon(R) Phi(TM) processor Family?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B

Package. ConfigTDP Control (R/W) See Table 2-24.

Parameters

ECX	MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);

Note: MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.

#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649

Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.

Parameters

ECX	MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);

Note: MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.

#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A

Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.

Parameters

ECX	MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);

Note: MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.

#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648

Package. Base TDP Ratio (R/O) See Table 2-24.

Parameters

ECX	MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);

Note: MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.

#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF

Core. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6 Residency Counter. (R/O).

Parameters

ECX	MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);

Note: MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.

#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690

Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency refers to processor core frequency).

Parameters

ECX	MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.

Example usage

MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);

Note: MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.

#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619

Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);

Note: MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.

#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B

Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);

Note: MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.

#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C

Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);

Note: MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.

#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618

Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);

Note: MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.

#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C

Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.

Parameters

ECX	MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.

Example usage

MSR_XEON_PHI_FEATURE_CONFIG_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);

Note: MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.

#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0

Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.

Parameters

ECX	MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.

Example usage

MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);

Note: MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.

#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C

Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.

Parameters

ECX	MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);

Note: MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.

#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491

Core. Capability Reporting Register of VM-Function Controls (R/O) See Table 2-2.

Parameters

ECX	MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);

Note: MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.

#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9

Thread. Last Branch Record Stack TOS (R/W).

Parameters

ECX	MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);

Note: MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.

#define MSR_XEON_PHI_LBR_SELECT 0x000001C8

Thread. Last Branch Record Filtering Select Register (R/W).

Parameters

ECX	MSR_XEON_PHI_LBR_SELECT (0x000001C8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);

Note: MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.

#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD

Thread. Last Exception Record From Linear IP (R).

Parameters

ECX	MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);

Note: MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.

#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE

Thread. Last Exception Record To Linear IP (R).

Parameters

ECX	MSR_XEON_PHI_LER_TO_LIP (0x000001DE)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);

Note: MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.

#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC

Module. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0 Residency Counter. (R/O).

Parameters

ECX	MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);

Note: MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.

#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD

Module. Module C6 Residency Counter. (R/O).

Parameters

ECX	MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);

Note: MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.

#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4

Miscellaneous Feature Control (R/W).

Parameters

ECX	MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.

Example usage

MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);
AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);

Note: MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.

#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140

Thread. MISC_FEATURE_ENABLES.

Parameters

ECX	MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.

Example usage

MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);
AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);

#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620

Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select.

Parameters

ECX	MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.

Example usage

MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);
AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);

#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6

Shared. Offcore Response Event Select Register (R/W).

Parameters

ECX	MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);

Note: MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.

#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7

Shared. Offcore Response Event Select Register (R/W).

Parameters

ECX	MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);

Note: MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.

#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1

Thread. See Table 2-2.

Parameters

ECX	MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);

Note: MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.

#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2 Residency Counter. (R/O).

Parameters

ECX	MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);

Note: MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.

#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3 Residency Counter. (R/O).

Parameters

ECX	MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);

Note: MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.

#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9

Package. Package C6 Residency Counter. (R/O).

Parameters

ECX	MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);

Note: MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.

#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA

Package. Package C7 Residency Counter. (R/O).

Parameters

ECX	MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);

Note: MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.

#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2

Module. C-State Configuration Control (R/W).

Parameters

ECX	MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.

Example usage

MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);

Note: MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.

#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611

Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".

Parameters

ECX	MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);

Note: MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.

#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613

Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".

Parameters

ECX	MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);

Note: MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.

#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614

Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL Domain.".

Parameters

ECX	MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);

Note: MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.

#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610

Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package RAPL Domain.".

Parameters

ECX	MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);

Note: MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.

#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE

Package. Platform Information Contains power management and other model specific features enumeration. See http://biosbits.org.

Parameters

ECX	MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.

Example usage

MSR_XEON_PHI_PLATFORM_INFO_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);

Note: MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.

#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4

Module. Power Management IO Redirection in C-state (R/W).

Parameters

ECX	MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.

Example usage

MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);

Note: MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.

#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639

Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters

ECX	MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);

Note: MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.

#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638

Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters

ECX	MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);

Note: MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.

#define MSR_XEON_PHI_PPIN 0x0000004F

Package. Protected Processor Inventory Number (R/O). Protected Processor Inventory Number (R/O) A unique value within a given CPUID family/model/stepping signature that a privileged inventory initialization agent can access to identify each physical processor, when access to MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if MSR_PPIN_CTL[bits 1:0] = '10b'.

Parameters

ECX	MSR_XEON_PHI_PPIN (0x0000004F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);

#define MSR_XEON_PHI_PPIN_CTL 0x0000004E

Package. Protected Processor Inventory Number Enable Control (R/W).

Parameters

ECX	MSR_XEON_PHI_PPIN_CTL (0x0000004E)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.

Example usage

MSR_XEON_PHI_PPIN_CTL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);
AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);

#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606

Package. Unit Multipliers used in RAPL Interfaces (R/O).

Parameters

ECX	MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.

Example usage

MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);

Note: MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.

#define MSR_XEON_PHI_SMI_COUNT 0x00000034

Thread. SMI Counter (R/O).

Parameters

ECX	MSR_XEON_PHI_SMI_COUNT (0x00000034)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.

Example usage

MSR_XEON_PHI_SMI_COUNT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);

Note: MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.

#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D

THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM.

Parameters

ECX	MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.

Example usage

MSR_XEON_PHI_SMM_MCA_CAP_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);
AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);

Note: MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.

#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2

Package.

Parameters

ECX	MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.

Example usage

MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);

Note: MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.

#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C

Package. ConfigTDP Control (R/W) See Table 2-24.

Parameters

ECX	MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);

Note: MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.

#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD

Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).

Parameters

ECX	MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.

Example usage

MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);

Note: MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.

Data Structures

Macros

Detailed Description

Macro Definition Documentation