Data Fields
struct {
UINT32 FastStrings:1

UINT32 Reserved1:2

UINT32 AutomaticThermalControlCircuit:1

UINT32 Reserved2:3

UINT32 PerformanceMonitoring:1

UINT32 Reserved3:3

UINT32 BTS:1

UINT32 PEBS:1

UINT32 Reserved4:3

UINT32 EIST:1

UINT32 Reserved5:1

UINT32 MONITOR:1

UINT32 Reserved6:3

UINT32 LimitCpuidMaxval:1

UINT32 xTPR_Message_Disable:1

UINT32 Reserved7:8

UINT32 Reserved8:2

UINT32 XD:1

UINT32 Reserved9:3

UINT32 TurboModeDisable:1

UINT32 Reserved10:25

}	Bits

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_PHI_IA32_MISC_ENABLE

Field Documentation

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value is 1.

struct { ... } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Branch Trace Storage Unavailable (RO).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Fast-Strings Enable.

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Limit CPUID Maxval (R/W).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] ENABLE MONITOR FSM (R/W).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Processor Event Based Sampling Unavailable (RO).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Performance Monitoring Available (R).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved1

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved10

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved2

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved3

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved4

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved5

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved6

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved7

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved8

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved9

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::TurboModeDisable

[Bit 38] Turbo Mode Disable (R/W).

UINT64 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] XD Bit Disable (R/W).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] xTPR Message Disable (R/W).