MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Union Reference

Data Fields
struct {
UINT32   DCUHardwarePrefetcherDisable:1
UINT32   L2HardwarePrefetcherDisable:1
UINT32   Reserved1:30
UINT32   Reserved2:32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_PHI_MISC_FEATURE_CONTROL

Field Documentation

struct { ... } MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::DCUHardwarePrefetcherDisable

[Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher.

UINT32 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::L2HardwarePrefetcherDisable

[Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher.

UINT32 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::Reserved1

UINT32 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::Reserved2

UINT32 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value