MSR_XEON_PHI_PLATFORM_INFO_REGISTER Union Reference

Data Fields
struct {
UINT32   Reserved1:8
UINT32   MaximumNonTurboRatio:8
UINT32   Reserved2:12
UINT32   RatioLimit:1
UINT32   TDPLimit:1
UINT32   Reserved3:2
UINT32   Reserved4:8
UINT32   MaximumEfficiencyRatio:8
UINT32   Reserved5:16
}	Bits
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_PHI_PLATFORM_INFO

Field Documentation

struct { ... } MSR_XEON_PHI_PLATFORM_INFO_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::MaximumEfficiencyRatio

[Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the minimum ratio (maximum efficiency) that the processor can operates, in units of 100MHz.

UINT32 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::MaximumNonTurboRatio

[Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio of the frequency that invariant TSC runs at. Frequency = ratio * 100 MHz.

UINT32 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::RatioLimit

[Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limits for Turbo mode is enabled, and when set to 0, indicates Programmable Ratio Limits for Turbo mode is disabled.

UINT32 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::Reserved1

UINT32 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::Reserved2

UINT32 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::Reserved3

UINT32 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::Reserved4

UINT32 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::Reserved5

UINT32 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::TDPLimit

[Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limits for Turbo mode are programmable, and when set to 0, indicates TDP Limit for Turbo mode is not programmable.

UINT64 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::Uint64

All bit fields as a 64-bit value