Data Structures
union	MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER

union	MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER

union	MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER

union	MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER

union	MSR_PENTIUM_4_MCG_MISC_REGISTER

union	MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER

union	MSR_PENTIUM_4_PLATFORM_BRV_REGISTER

union	MSR_PENTIUM_4_PEBS_ENABLE_REGISTER

Macros
#define	IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel)

#define	MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006

#define	MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A

#define	MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B

#define	MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C

#define	MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C

#define	MSR_PENTIUM_4_MCG_RAX 0x00000180

#define	MSR_PENTIUM_4_MCG_RBX 0x00000181

#define	MSR_PENTIUM_4_MCG_RCX 0x00000182

#define	MSR_PENTIUM_4_MCG_RDX 0x00000183

#define	MSR_PENTIUM_4_MCG_RSI 0x00000184

#define	MSR_PENTIUM_4_MCG_RDI 0x00000185

#define	MSR_PENTIUM_4_MCG_RBP 0x00000186

#define	MSR_PENTIUM_4_MCG_RSP 0x00000187

#define	MSR_PENTIUM_4_MCG_RFLAGS 0x00000188

#define	MSR_PENTIUM_4_MCG_RIP 0x00000189

#define	MSR_PENTIUM_4_MCG_MISC 0x0000018A

#define	MSR_PENTIUM_4_MCG_R8 0x00000190

#define	MSR_PENTIUM_4_MCG_R9 0x00000191

#define	MSR_PENTIUM_4_MCG_R10 0x00000192

#define	MSR_PENTIUM_4_MCG_R11 0x00000193

#define	MSR_PENTIUM_4_MCG_R12 0x00000194

#define	MSR_PENTIUM_4_MCG_R13 0x00000195

#define	MSR_PENTIUM_4_MCG_R14 0x00000196

#define	MSR_PENTIUM_4_MCG_R15 0x00000197

#define	MSR_PENTIUM_4_THERM2_CTL 0x0000019D

#define	MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0

#define	MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1

#define	MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7

#define	MSR_PENTIUM_4_LER_TO_LIP 0x000001D8

#define	MSR_PENTIUM_4_DEBUGCTLA 0x000001D9

#define	MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA

#define	MSR_PENTIUM_4_BSU_ESCR0 0x000003A0

#define	MSR_PENTIUM_4_BSU_ESCR1 0x000003A1

#define	MSR_PENTIUM_4_FSB_ESCR0 0x000003A2

#define	MSR_PENTIUM_4_FSB_ESCR1 0x000003A3

#define	MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4

#define	MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5

#define	MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6

#define	MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7

#define	MSR_PENTIUM_4_DAC_ESCR0 0x000003A8

#define	MSR_PENTIUM_4_DAC_ESCR1 0x000003A9

#define	MSR_PENTIUM_4_MOB_ESCR0 0x000003AA

#define	MSR_PENTIUM_4_MOB_ESCR1 0x000003AB

#define	MSR_PENTIUM_4_PMH_ESCR0 0x000003AC

#define	MSR_PENTIUM_4_PMH_ESCR1 0x000003AD

#define	MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE

#define	MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF

#define	MSR_PENTIUM_4_U2L_ESCR0 0x000003B0

#define	MSR_PENTIUM_4_U2L_ESCR1 0x000003B1

#define	MSR_PENTIUM_4_BPU_ESCR0 0x000003B2

#define	MSR_PENTIUM_4_BPU_ESCR1 0x000003B3

#define	MSR_PENTIUM_4_IS_ESCR0 0x000003B4

#define	MSR_PENTIUM_4_IS_ESCR1 0x000003B5

#define	MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6

#define	MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7

#define	MSR_PENTIUM_4_CRU_ESCR0 0x000003B8

#define	MSR_PENTIUM_4_CRU_ESCR1 0x000003B9

#define	MSR_PENTIUM_4_IQ_ESCR0 0x000003BA

#define	MSR_PENTIUM_4_IQ_ESCR1 0x000003BB

#define	MSR_PENTIUM_4_RAT_ESCR0 0x000003BC

#define	MSR_PENTIUM_4_RAT_ESCR1 0x000003BD

#define	MSR_PENTIUM_4_SSU_ESCR0 0x000003BE

#define	MSR_PENTIUM_4_MS_ESCR0 0x000003C0

#define	MSR_PENTIUM_4_MS_ESCR1 0x000003C1

#define	MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2

#define	MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3

#define	MSR_PENTIUM_4_TC_ESCR0 0x000003C4

#define	MSR_PENTIUM_4_TC_ESCR1 0x000003C5

#define	MSR_PENTIUM_4_IX_ESCR0 0x000003C8

#define	MSR_PENTIUM_4_IX_ESCR1 0x000003C9

#define	MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0

#define	MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1

#define	MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2

#define	MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC

#define	MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD

#define	MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE

#define	MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF

#define	MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0

#define	MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1

#define	MSR_PENTIUM_4_IFSB_CTL6 0x000107D2

#define	MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3

#define	MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC

#define	MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD

#define	MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE

#define	MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF

#define	MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0

#define	MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1

#define	MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2

#define	MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3


#define	MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB

#define	MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC

#define	MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD

#define	MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE


#define	MSR_PENTIUM_4_BPU_COUNTER0 0x00000300

#define	MSR_PENTIUM_4_BPU_COUNTER1 0x00000301

#define	MSR_PENTIUM_4_BPU_COUNTER2 0x00000302

#define	MSR_PENTIUM_4_BPU_COUNTER3 0x00000303


#define	MSR_PENTIUM_4_MS_COUNTER0 0x00000304

#define	MSR_PENTIUM_4_MS_COUNTER1 0x00000305

#define	MSR_PENTIUM_4_MS_COUNTER2 0x00000306

#define	MSR_PENTIUM_4_MS_COUNTER3 0x00000307


#define	MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308

#define	MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309

#define	MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A

#define	MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B


#define	MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C

#define	MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D

#define	MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E

#define	MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F

#define	MSR_PENTIUM_4_IQ_COUNTER4 0x00000310

#define	MSR_PENTIUM_4_IQ_COUNTER5 0x00000311


#define	MSR_PENTIUM_4_BPU_CCCR0 0x00000360

#define	MSR_PENTIUM_4_BPU_CCCR1 0x00000361

#define	MSR_PENTIUM_4_BPU_CCCR2 0x00000362

#define	MSR_PENTIUM_4_BPU_CCCR3 0x00000363


#define	MSR_PENTIUM_4_MS_CCCR0 0x00000364

#define	MSR_PENTIUM_4_MS_CCCR1 0x00000365

#define	MSR_PENTIUM_4_MS_CCCR2 0x00000366

#define	MSR_PENTIUM_4_MS_CCCR3 0x00000367


#define	MSR_PENTIUM_4_FLAME_CCCR0 0x00000368

#define	MSR_PENTIUM_4_FLAME_CCCR1 0x00000369

#define	MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A

#define	MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B


#define	MSR_PENTIUM_4_IQ_CCCR0 0x0000036C

#define	MSR_PENTIUM_4_IQ_CCCR1 0x0000036D

#define	MSR_PENTIUM_4_IQ_CCCR2 0x0000036E

#define	MSR_PENTIUM_4_IQ_CCCR3 0x0000036F

#define	MSR_PENTIUM_4_IQ_CCCR4 0x00000370

#define	MSR_PENTIUM_4_IQ_CCCR5 0x00000371


#define	MSR_PENTIUM_4_ALF_ESCR0 0x000003CA

#define	MSR_PENTIUM_4_ALF_ESCR1 0x000003CB

#define	MSR_PENTIUM_4_CRU_ESCR2 0x000003CC

#define	MSR_PENTIUM_4_CRU_ESCR3 0x000003CD

#define	MSR_PENTIUM_4_CRU_ESCR4 0x000003E0

#define	MSR_PENTIUM_4_CRU_ESCR5 0x000003E1


#define	MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680

#define	MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681

#define	MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682

#define	MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683

#define	MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684

#define	MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685

#define	MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686

#define	MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687

#define	MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688

#define	MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689

#define	MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A

#define	MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B

#define	MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C

#define	MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D

#define	MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E

#define	MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F


#define	MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0

#define	MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1

#define	MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2

#define	MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3

#define	MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4

#define	MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5

#define	MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6

#define	MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7

#define	MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8

#define	MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9

#define	MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA

#define	MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB

#define	MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC

#define	MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD

#define	MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE

#define	MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF

Detailed Description

MSR Definitions for Pentium(R) 4 Processors.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_PENTIUM_4_PROCESSOR	(	DisplayFamily,
		DisplayModel
	)

Value:

(DisplayFamily == 0x0F \

)

Is Pentium(R) 4 Processors?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

#define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_ALF_ESCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);

Note: MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM. MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM. MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM. MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM. MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM. MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.

#define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_ALF_ESCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);

Note: MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM. MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM. MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM. MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM. MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM. MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.

#define MSR_PENTIUM_4_BPU_CCCR0 0x00000360

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_BPU_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);

Note: MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM. MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM. MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM. MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.

#define MSR_PENTIUM_4_BPU_CCCR1 0x00000361

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_BPU_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);

Note: MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM. MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM. MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM. MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.

#define MSR_PENTIUM_4_BPU_CCCR2 0x00000362

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_BPU_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);

Note: MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM. MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM. MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM. MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.

#define MSR_PENTIUM_4_BPU_CCCR3 0x00000363

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_BPU_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);

Note: MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM. MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM. MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM. MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.

#define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_BPU_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);

Note: MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM. MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM. MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM. MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.

#define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_BPU_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);

Note: MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM. MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM. MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM. MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.

#define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_BPU_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);

Note: MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM. MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM. MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM. MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.

#define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_BPU_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);

Note: MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM. MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM. MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM. MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.

#define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr);

Note: MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM.

#define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr);

Note: MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM.

#define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr);

Note: MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM.

#define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr);

Note: MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM.

#define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr);

Note: MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM.

#define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr);

Note: MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM.

#define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_ALF_ESCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);

Note: MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM. MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM. MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM. MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM. MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM. MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.

#define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_ALF_ESCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);

Note: MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM. MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM. MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM. MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM. MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM. MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.

#define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_ALF_ESCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);

Note: MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM. MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM. MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM. MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM. MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM. MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.

#define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_ALF_ESCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);

Note: MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM. MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM. MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM. MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM. MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM. MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.

#define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr);

Note: MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM.

#define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr);

Note: MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM.

#define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9

0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section. See Section 17.13.1, "MSR_DEBUGCTLA MSR.".

Parameters

ECX	MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA);
AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr);

Note: MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM.

#define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C

2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of this MSR varies according to the MODEL value in the CPUID version information. The following bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding equal or greater than 2. (R) The field Indicates the current processor frequency configuration.

Parameters

ECX	MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C)
EAX	Lower 32-bits of MSR value. Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.

Example usage

MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);

Note: MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM.

#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C

0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of this MSR varies according to the MODEL value of the CPUID version information. This bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding less than 2. Indicates current processor frequency configuration.

Parameters

ECX	MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C)
EAX	Lower 32-bits of MSR value. Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.

Example usage

MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);

Note: MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM.

#define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A

0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.

Parameters

ECX	MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A)
EAX	Lower 32-bits of MSR value. Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.

Example usage

MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);
AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);

Note: MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM.

#define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B

0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W) Enables and disables processor features.

Parameters

ECX	MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B)
EAX	Lower 32-bits of MSR value. Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.

Example usage

MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);
AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);

Note: MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM.

#define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0

3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.".

Parameters

ECX	MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0);
AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr);

Note: MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM.

#define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1

3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W).

Parameters

ECX	MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1);
AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr);

Note: MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM.

#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC

Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte L3 Cache.".

Parameters

ECX	MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0);
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr);

Note: MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.

#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD

Shared. GBUSQ Event Control and Counter Register (R/W).

Parameters

ECX	MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1);
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr);

Note: MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.

#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE

Shared. GSNPQ Event Control and Counter Register (R/W) See Section 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte L3 Cache.".

Parameters

ECX	MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2);
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr);

Note: MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.

#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF

Shared. GSNPQ Event Control and Counter Register (R/W).

Parameters

ECX	MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3);
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr);

Note: MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.

#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0

Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte L3 Cache.".

Parameters

ECX	MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4);
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr);

Note: MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.

#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1

Shared. FSB Event Control and Counter Register (R/W).

Parameters

ECX	MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5);
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr);

Note: MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.

#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2

Shared. FSB Event Control and Counter Register (R/W).

Parameters

ECX	MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6);
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr);

Note: MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.

#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3

Shared. FSB Event Control and Counter Register (R/W).

Parameters

ECX	MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7);
AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr);

Note: MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.

#define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr);

Note: MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM.

#define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr);

Note: MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM.

#define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_FLAME_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);

Note: MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM. MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM. MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM. MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.

#define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_FLAME_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);

Note: MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM. MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM. MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM. MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.

#define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_FLAME_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);

Note: MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM. MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM. MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM. MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.

#define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_FLAME_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);

Note: MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM. MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM. MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM. MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.

#define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);

Note: MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM. MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM. MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM. MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.

#define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);

Note: MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM. MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM. MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM. MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.

#define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);

Note: MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM. MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM. MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM. MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.

#define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);

Note: MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM. MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM. MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM. MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.

#define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr);

Note: MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM.

#define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr);

Note: MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM.

#define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr);

Note: MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM.

#define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr);

Note: MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM.

#define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0

0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W).

Parameters

ECX	MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.

Example usage

MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64);

Note: MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.

#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006

3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range Determination.".

Parameters

ECX	MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);
AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);

Note: MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM.

#define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC

3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.".

Parameters

ECX	MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0);
AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr);

Note: MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM.

#define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD

3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W).

Parameters

ECX	MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1);
AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr);

Note: MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM.

#define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3

3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.".

Parameters

ECX	MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7);
AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr);

Note: MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM.

#define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2

3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.".

Parameters

ECX	MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6);
AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr);

Note: MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM.

#define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE

3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.".

Parameters

ECX	MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0);
AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr);

Note: MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM.

#define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF

3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W).

Parameters

ECX	MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1);
AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr);

Note: MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM.

#define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_IQ_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);

Note: MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM. MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM. MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM. MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM. MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM. MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.

#define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_IQ_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);

Note: MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM. MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM. MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM. MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM. MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM. MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.

#define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_IQ_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);

Note: MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM. MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM. MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM. MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM. MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM. MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.

#define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_IQ_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);

Note: MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM. MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM. MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM. MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM. MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM. MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.

#define MSR_PENTIUM_4_IQ_CCCR4 0x00000370

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_IQ_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);

Note: MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM. MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM. MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM. MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM. MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM. MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.

#define MSR_PENTIUM_4_IQ_CCCR5 0x00000371

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_IQ_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);

Note: MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM. MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM. MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM. MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM. MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM. MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.

#define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_IQ_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);

Note: MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM. MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM. MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM. MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM. MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM. MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.

#define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_IQ_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);

Note: MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM. MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM. MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM. MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM. MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM. MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.

#define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_IQ_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);

Note: MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM. MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM. MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM. MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM. MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM. MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.

#define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_IQ_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);

Note: MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM. MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM. MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM. MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM. MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM. MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.

#define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_IQ_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);

Note: MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM. MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM. MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM. MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM. MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM. MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.

#define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_IQ_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);

Note: MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM. MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM. MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM. MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM. MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM. MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.

#define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA

0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-02H.

Parameters

ECX	MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr);

Note: MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM.

#define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB

0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-02H.

Parameters

ECX	MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr);

Note: MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM.

#define MSR_PENTIUM_4_IS_ESCR0 0x000003B4

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr);

Note: MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM.

#define MSR_PENTIUM_4_IS_ESCR1 0x000003B5

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr);

Note: MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM.

#define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr);

Note: MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM.

#define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr);

Note: MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM.

#define MSR_PENTIUM_4_IX_ESCR0 0x000003C8

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr);

Note: MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM.

#define MSR_PENTIUM_4_IX_ESCR1 0x000003C9

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr);

Note: MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB

0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record registers on the last branch record stack. It contains pointers to the source and destination instruction for one of the last four branches, exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC

0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record registers on the last branch record stack. It contains pointers to the source and destination instruction for one of the last four branches, exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD

0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record registers on the last branch record stack. It contains pointers to the source and destination instruction for one of the last four branches, exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE

0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record registers on the last branch record stack. It contains pointers to the source and destination instruction for one of the last four branches, exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9

3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.".

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA

0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an index (0-3 or 0-15) that points to the top of the last branch record stack (that is, that points the index of the MSR containing the most recent branch record). See Section 17.13.2, "LBR Stack for Processors Based on Intel NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.

Parameters

ECX	MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr);

Note: MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.

#define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7

0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.13.3, "Last Exception Records.". Unique. From Linear IP Linear address of the last branch instruction (If IA-32e mode is active). From Linear IP Linear address of the last branch instruction. Reserved.

Parameters

ECX	MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP);

Note: MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.

#define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8

0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.13.3, "Last Exception Records.". Unique. From Linear IP Linear address of the target of the last branch instruction (If IA-32e mode is active). From Linear IP Linear address of the target of the last branch instruction. Reserved.

Parameters

ECX	MSR_PENTIUM_4_LER_TO_LIP (0x000001D8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP);

Note: MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.

#define MSR_PENTIUM_4_MCG_MISC 0x0000018A

0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.".

Parameters

ECX	MSR_PENTIUM_4_MCG_MISC (0x0000018A)
EAX	Lower 32-bits of MSR value. Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.

Example usage

MSR_PENTIUM_4_MCG_MISC_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64);

Note: MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM.

#define MSR_PENTIUM_4_MCG_R10 0x00000192

0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error.

Parameters

ECX	MSR_PENTIUM_4_MCG_R10 (0x00000192)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr);

Note: MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM.

#define MSR_PENTIUM_4_MCG_R11 0x00000193

0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error.

Parameters

ECX	MSR_PENTIUM_4_MCG_R11 (0x00000193)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr);

Note: MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM.

#define MSR_PENTIUM_4_MCG_R12 0x00000194

0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error.

Parameters

ECX	MSR_PENTIUM_4_MCG_R12 (0x00000194)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr);

Note: MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM.

#define MSR_PENTIUM_4_MCG_R13 0x00000195

0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error.

Parameters

ECX	MSR_PENTIUM_4_MCG_R13 (0x00000195)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr);

Note: MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM.

#define MSR_PENTIUM_4_MCG_R14 0x00000196

0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error.

Parameters

ECX	MSR_PENTIUM_4_MCG_R14 (0x00000196)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr);

Note: MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM.

#define MSR_PENTIUM_4_MCG_R15 0x00000197

0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error.

Parameters

ECX	MSR_PENTIUM_4_MCG_R15 (0x00000197)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr);

Note: MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM.

#define MSR_PENTIUM_4_MCG_R8 0x00000190

0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error.

Parameters

ECX	MSR_PENTIUM_4_MCG_R8 (0x00000190)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr);

Note: MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM.

#define MSR_PENTIUM_4_MCG_R9 0x00000191

0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error.

Parameters

ECX	MSR_PENTIUM_4_MCG_R9 (0x00000191)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr);

Note: MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM.

#define MSR_PENTIUM_4_MCG_RAX 0x00000180

0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data.

Parameters

ECX	MSR_PENTIUM_4_MCG_RAX (0x00000180)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);

Note: MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM.

#define MSR_PENTIUM_4_MCG_RBP 0x00000186

0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data.

Parameters

ECX	MSR_PENTIUM_4_MCG_RBP (0x00000186)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);

Note: MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM.

#define MSR_PENTIUM_4_MCG_RBX 0x00000181

0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data.

Parameters

ECX	MSR_PENTIUM_4_MCG_RBX (0x00000181)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);

Note: MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM.

#define MSR_PENTIUM_4_MCG_RCX 0x00000182

0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data.

Parameters

ECX	MSR_PENTIUM_4_MCG_RCX (0x00000182)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);

Note: MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM.

#define MSR_PENTIUM_4_MCG_RDI 0x00000185

0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data.

Parameters

ECX	MSR_PENTIUM_4_MCG_RDI (0x00000185)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);

Note: MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM.

#define MSR_PENTIUM_4_MCG_RDX 0x00000183

0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data.

Parameters

ECX	MSR_PENTIUM_4_MCG_RDX (0x00000183)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);

Note: MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM.

#define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188

0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data.

Parameters

ECX	MSR_PENTIUM_4_MCG_RFLAGS (0x00000188)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);

Note: MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM.

#define MSR_PENTIUM_4_MCG_RIP 0x00000189

0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data.

Parameters

ECX	MSR_PENTIUM_4_MCG_RIP (0x00000189)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);

Note: MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM.

#define MSR_PENTIUM_4_MCG_RSI 0x00000184

0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data.

Parameters

ECX	MSR_PENTIUM_4_MCG_RSI (0x00000184)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);

Note: MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM.

#define MSR_PENTIUM_4_MCG_RSP 0x00000187

0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data.

Parameters

ECX	MSR_PENTIUM_4_MCG_RSP (0x00000187)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);
AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);

Note: MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM.

#define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr);

Note: MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM.

#define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr);

Note: MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM.

#define MSR_PENTIUM_4_MS_CCCR0 0x00000364

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_MS_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);

Note: MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM. MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM. MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM. MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.

#define MSR_PENTIUM_4_MS_CCCR1 0x00000365

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_MS_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);

Note: MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM. MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM. MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM. MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.

#define MSR_PENTIUM_4_MS_CCCR2 0x00000366

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_MS_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);

Note: MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM. MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM. MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM. MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.

#define MSR_PENTIUM_4_MS_CCCR3 0x00000367

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_MS_CCCRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);

Note: MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM. MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM. MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM. MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.

#define MSR_PENTIUM_4_MS_COUNTER0 0x00000304

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_MS_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);

Note: MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM. MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM. MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM. MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.

#define MSR_PENTIUM_4_MS_COUNTER1 0x00000305

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_MS_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);

Note: MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM. MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM. MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM. MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.

#define MSR_PENTIUM_4_MS_COUNTER2 0x00000306

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_MS_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);

Note: MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM. MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM. MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM. MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.

#define MSR_PENTIUM_4_MS_COUNTER3 0x00000307

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".

Parameters

ECX	MSR_PENTIUM_4_MS_COUNTERn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);
AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);

Note: MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM. MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM. MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM. MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.

#define MSR_PENTIUM_4_MS_ESCR0 0x000003C0

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr);

Note: MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM.

#define MSR_PENTIUM_4_MS_ESCR1 0x000003C1

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr);

Note: MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM.

#define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1

0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W) Controls the enabling of processor event sampling and replay tagging.

Parameters

ECX	MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)
EAX	Lower 32-bits of MSR value. Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.

Example usage

MSR_PENTIUM_4_PEBS_ENABLE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE);
AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64);

Note: MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.

#define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2

0, 1, 2, 3, 4, 6. Shared. See Table 19-36.

Parameters

ECX	MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT);
AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr);

Note: MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM.

#define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1

3, 4, 6. Shared. Platform Feature Requirements (R).

Parameters

ECX	MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1)
EAX	Lower 32-bits of MSR value. Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.

Example usage

MSR_PENTIUM_4_PLATFORM_BRV_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV);

Note: MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM.

#define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr);

Note: MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM.

#define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr);

Note: MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM.

#define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr);

Note: MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM.

#define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr);

Note: MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM.

#define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr);

Note: MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM.

#define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr);

Note: MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM.

#define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr);

Note: MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM.

#define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr);

Note: MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM.

#define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr);

Note: MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM.

#define MSR_PENTIUM_4_TC_ESCR0 0x000003C4

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr);

Note: MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM.

#define MSR_PENTIUM_4_TC_ESCR1 0x000003C5

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr);

Note: MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM.

#define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT);
AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr);

Note: MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM.

#define MSR_PENTIUM_4_THERM2_CTL 0x0000019D

Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors: When read, specifies the value of the target TM2 transition last written. When set, it sets the next target value for TM2 transition. 4, 6. Shared. For Family F, Model 4 and Model 6 processors: When read, specifies the value of the target TM2 transition last written. Writes may cause #GP exceptions.

Parameters

ECX	MSR_PENTIUM_4_THERM2_CTL (0x0000019D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL);
AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr);

Note: MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.

#define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0);
AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr);

Note: MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM.

#define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1

0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".

Parameters

ECX	MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1);
AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr);

Note: MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM.

Data Structures

Macros

Detailed Description

Macro Definition Documentation