MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Union Reference

Data Fields
struct {
UINT32   EventNum:13
UINT32   Reserved1:11
UINT32   UOP:1
UINT32   ENABLE_PEBS_MY_THR:1
UINT32   ENABLE_PEBS_OTH_THR:1
UINT32   Reserved2:5
UINT32   Reserved3:32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_PENTIUM_4_PEBS_ENABLE

Field Documentation

struct { ... } MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::ENABLE_PEBS_MY_THR

[Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical processor when set; disables PEBS when clear (default). See Section 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target logical processor. This bit is called ENABLE_PEBS in IA-32 processors that do not support Intel HyperThreading Technology.

UINT32 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::ENABLE_PEBS_OTH_THR

[Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical processor when set; disables PEBS when clear (default). See Section 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target logical processor. This bit is reserved for IA-32 processors that do not support Intel Hyper-Threading Technology.

UINT32 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::EventNum

[Bits 12:0] See Table 19-36.

UINT32 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::Reserved1

UINT32 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::Reserved2

UINT32 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::Reserved3

UINT32 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::UOP

[Bit 24] UOP Tag Enables replay tagging when set.