MSR information returned for MSR index MSR_PENTIUM_4_IA32_MISC_ENABLE
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::AdjacentCacheLinePrefetchDisable |
[Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1, the processor fetches the cache line of the 128-byte sector containing currently required data. When set to 0, the processor fetches both cache lines in the sector. Single processor platforms should not set this bit. Server platforms should set or clear this bit based on platform performance observed in validation and testing. BIOS may contain a setup option that controls the setting of this bit.
| struct { ... } MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::Bits |
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::BTS |
[Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See Table 2-2. When set, the processor does not support branch trace storage (BTS); when clear, BTS is supported.
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::FastStrings |
[Bit 0] Fast-Strings Enable. See Table 2-2.
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::FERR |
[Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt reporting through the FERR# pin is enabled; when clear, this interrupt reporting function is disabled. When this flag is set and the processor is in the stop-clock state (STPCLK# is asserted), asserting the FERR# pin signals to the processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI, SMI#, or RESET#) is pending and that the processor should return to normal operation to handle the interrupt. This flag does not affect the normal operation of the FERR# pin (to indicate an unmasked floatingpoint error) when the STPCLK# pin is not asserted.
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::FPU |
[Bit 2] x87 FPU Fopcode Compatibility Mode Enable.
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::L1DataCacheContextMode |
[Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache is placed in shared mode; when clear (default), the cache is placed in adaptive mode. This bit is only enabled for IA-32 processors that support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data
Cache Context Mode." When L1 is running in adaptive mode and CR3s are identical, data in L1 is shared across logical processors. Otherwise, L1 is not shared and cache use is competitive. If the Context ID feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1, the ability to switch modes is not supported. BIOS must not alter the contents of IA32_MISC_ENABLE[24].
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval |
[Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this can cause unexpected behavior to software that depends on the availability of CPUID leaves greater than 3.
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::MONITOR |
[Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2.
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::PEBS |
[Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable (R) See Table 2-2. When set, the processor does not support processor event-based sampling (PEBS); when clear, PEBS is supported.
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring |
[Bit 7] Performance Monitoring Available (R) See Table 2-2.
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::PrefetchQueueDisable |
[Bit 9] Prefetch Queue Disable When set, disables the prefetch queue. When clear (default), enables the prefetch queue.
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::Reserved1 |
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::Reserved2 |
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::Reserved3 |
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::Reserved4 |
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::Reserved5 |
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::Reserved6 |
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::Reserved7 |
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::SplitLockDisable |
[Bit 4] Split-Lock Disable When set, the bit causes an #AC exception to be issued instead of a split-lock cycle. Operating systems that set this bit must align system structures to avoid split-lock scenarios. When the bit is clear (default), normal split-locks are issued to the bus. This debug feature is specific to the Pentium 4 processor.
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::SuppressLockEnable |
[Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is suppressed during a Split Lock access. When clear (default), LOCK is not suppressed.
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::ThirdLevelCacheDisable |
[Bit 6] Third-Level Cache Disable (R/W) When set, the third-level cache is disabled; when clear (default) the third-level cache is enabled. This flag is reserved for processors that do not have a third-level cache. Note that the bit controls only the third-level cache; and only if overall caching is enabled through the CD flag of control register CR0, the page-level cache controls, and/or the MTRRs. See Section 11.5.4, "Disabling and Enabling the L3 Cache.".
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::TM1 |
[Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal
Monitor," and see Table 2-2.
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::TM2 |
[Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal sensor indicates that the die temperature is at the predetermined threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce the bus to core ratio and voltage according to the value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the processor does not change the VID signals or the bus to core ratio when the processor enters a thermal managed state. If the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then this feature is not supported and BIOS must not alter the contents of this bit location. The processor is operating out of spec if both this bit and the TM1 bit are set to disabled states.
| UINT64 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::Uint64 |
All bit fields as a 64-bit value
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::XD |
[Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
| UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable |
[Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
1.8.6 
