P6Msr.h File Reference

Data Structures
union	MSR_P6_IA32_PLATFORM_ID_REGISTER
union	MSR_P6_APIC_BASE_REGISTER
union	MSR_P6_EBL_CR_POWERON_REGISTER
union	MSR_P6_TEST_CTL_REGISTER
union	MSR_P6_BBL_CR_ADDR_REGISTER
union	MSR_P6_BBL_CR_CTL_REGISTER
union	MSR_P6_BBL_CR_CTL3_REGISTER
union	MSR_P6_PERFEVTSEL_REGISTER
union	MSR_P6_DEBUGCTLMSR_REGISTER
union	MSR_P6_MTRRDEFTYPE_REGISTER
union	MSR_P6_MC_STATUS_REGISTER

Macros
#define	IS_P6_PROCESSOR(DisplayFamily, DisplayModel)
#define	MSR_P6_P5_MC_ADDR   0x00000000
#define	MSR_P6_P5_MC_TYPE   0x00000001
#define	MSR_P6_TSC   0x00000010
#define	MSR_P6_IA32_PLATFORM_ID   0x00000017
#define	MSR_P6_APIC_BASE   0x0000001B
#define	MSR_P6_EBL_CR_POWERON   0x0000002A
#define	MSR_P6_TEST_CTL   0x00000033
#define	MSR_P6_BIOS_UPDT_TRIG   0x00000079
#define	MSR_P6_BIOS_SIGN   0x0000008B
#define	MSR_P6_MTRRCAP   0x000000FE
#define	MSR_P6_BBL_CR_ADDR   0x00000116
#define	MSR_P6_BBL_CR_DECC   0x00000118
#define	MSR_P6_BBL_CR_CTL   0x00000119
#define	MSR_P6_BBL_CR_TRIG   0x0000011A
#define	MSR_P6_BBL_CR_BUSY   0x0000011B
#define	MSR_P6_BBL_CR_CTL3   0x0000011E
#define	MSR_P6_SYSENTER_CS_MSR   0x00000174
#define	MSR_P6_SYSENTER_ESP_MSR   0x00000175
#define	MSR_P6_SYSENTER_EIP_MSR   0x00000176
#define	MSR_P6_MCG_CAP   0x00000179
#define	MSR_P6_MCG_STATUS   0x0000017A
#define	MSR_P6_MCG_CTL   0x0000017B
#define	MSR_P6_DEBUGCTLMSR   0x000001D9
#define	MSR_P6_LASTBRANCHFROMIP   0x000001DB
#define	MSR_P6_LASTBRANCHTOIP   0x000001DC
#define	MSR_P6_LASTINTFROMIP   0x000001DD
#define	MSR_P6_LASTINTTOIP   0x000001DE
#define	MSR_P6_MTRRFIX64K_00000   0x00000250
#define	MSR_P6_MTRRFIX16K_80000   0x00000258
#define	MSR_P6_MTRRFIX16K_A0000   0x00000259
#define	MSR_P6_MTRRFIX4K_C0000   0x00000268
#define	MSR_P6_MTRRFIX4K_C8000   0x00000269
#define	MSR_P6_MTRRFIX4K_D0000   0x0000026A
#define	MSR_P6_MTRRFIX4K_D8000   0x0000026B
#define	MSR_P6_MTRRFIX4K_E0000   0x0000026C
#define	MSR_P6_MTRRFIX4K_E8000   0x0000026D
#define	MSR_P6_MTRRFIX4K_F0000   0x0000026E
#define	MSR_P6_MTRRFIX4K_F8000   0x0000026F
#define	MSR_P6_MTRRDEFTYPE   0x000002FF
#define	MSR_P6_BBL_CR_D0   0x00000088
#define	MSR_P6_BBL_CR_D1   0x00000089
#define	MSR_P6_BBL_CR_D2   0x0000008A
#define	MSR_P6_PERFCTR0   0x000000C1
#define	MSR_P6_PERFCTR1   0x000000C2
#define	MSR_P6_PERFEVTSEL0   0x00000186
#define	MSR_P6_PERFEVTSEL1   0x00000187
#define	MSR_P6_MTRRPHYSBASE0   0x00000200
#define	MSR_P6_MTRRPHYSBASE1   0x00000202
#define	MSR_P6_MTRRPHYSBASE2   0x00000204
#define	MSR_P6_MTRRPHYSBASE3   0x00000206
#define	MSR_P6_MTRRPHYSBASE4   0x00000208
#define	MSR_P6_MTRRPHYSBASE5   0x0000020A
#define	MSR_P6_MTRRPHYSBASE6   0x0000020C
#define	MSR_P6_MTRRPHYSBASE7   0x0000020E
#define	MSR_P6_MTRRPHYSMASK0   0x00000201
#define	MSR_P6_MTRRPHYSMASK1   0x00000203
#define	MSR_P6_MTRRPHYSMASK2   0x00000205
#define	MSR_P6_MTRRPHYSMASK3   0x00000207
#define	MSR_P6_MTRRPHYSMASK4   0x00000209
#define	MSR_P6_MTRRPHYSMASK5   0x0000020B
#define	MSR_P6_MTRRPHYSMASK6   0x0000020D
#define	MSR_P6_MTRRPHYSMASK7   0x0000020F
#define	MSR_P6_MC0_CTL   0x00000400
#define	MSR_P6_MC1_CTL   0x00000404
#define	MSR_P6_MC2_CTL   0x00000408
#define	MSR_P6_MC3_CTL   0x00000410
#define	MSR_P6_MC4_CTL   0x0000040C
#define	MSR_P6_MC0_STATUS   0x00000401
#define	MSR_P6_MC1_STATUS   0x00000405
#define	MSR_P6_MC2_STATUS   0x00000409
#define	MSR_P6_MC3_STATUS   0x00000411
#define	MSR_P6_MC4_STATUS   0x0000040D
#define	MSR_P6_MC0_ADDR   0x00000402
#define	MSR_P6_MC1_ADDR   0x00000406
#define	MSR_P6_MC2_ADDR   0x0000040A
#define	MSR_P6_MC3_ADDR   0x00000412
#define	MSR_P6_MC4_ADDR   0x0000040E
#define	MSR_P6_MC0_MISC   0x00000403
#define	MSR_P6_MC1_MISC   0x00000407
#define	MSR_P6_MC2_MISC   0x0000040B
#define	MSR_P6_MC3_MISC   0x00000413
#define	MSR_P6_MC4_MISC   0x0000040F

Detailed Description

MSR Definitions for P6 Family Processors.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:

Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_P6_PROCESSOR	(		DisplayFamily,
			DisplayModel
	)

Value:

(DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x03 || \
    DisplayModel == 0x05 || \
    DisplayModel == 0x07 || \
    DisplayModel == 0x08 || \
    DisplayModel == 0x0A || \
    DisplayModel == 0x0B \
    ) \
   )

Is P6 Family Processors?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

#define MSR_P6_APIC_BASE   0x0000001B

Section 10.4.4, "Local APIC Status and Location.".

Parameters

ECX	MSR_P6_APIC_BASE (0x0000001B)
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_APIC_BASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_APIC_BASE_REGISTER.

Example usage

MSR_P6_APIC_BASE_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);
AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);

Note

MSR_P6_APIC_BASE is defined as APIC_BASE in SDM.

#define MSR_P6_BBL_CR_ADDR   0x00000116

Address register: used to send specified address (A31-A3) to L2 during cache initialization accesses.

Parameters

ECX	MSR_P6_BBL_CR_ADDR (0x00000116)
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.

Example usage

MSR_P6_BBL_CR_ADDR_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);
AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);

Note

MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM.

#define MSR_P6_BBL_CR_BUSY   0x0000011B

Busy register: indicates when a cache configuration accesses L2 command is in progress. D[0] = 1 = BUSY.

Parameters

ECX	MSR_P6_BBL_CR_BUSY (0x0000011B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);
AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);

Note

MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM.

#define MSR_P6_BBL_CR_CTL   0x00000119

Control register: used to program L2 commands to be issued via cache configuration accesses mechanism. Also receives L2 lookup response.

Parameters

ECX	MSR_P6_BBL_CR_CTL (0x00000119)
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_BBL_CR_CTL_REGISTER.

Example usage

MSR_P6_BBL_CR_CTL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);
AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);

Note

MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM.

#define MSR_P6_BBL_CR_CTL3   0x0000011E

Control register 3: used to configure the L2 Cache.

Parameters

ECX	MSR_P6_BBL_CR_CTL3 (0x0000011E)
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.

Example usage

MSR_P6_BBL_CR_CTL3_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);
AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);

Note

MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM.

#define MSR_P6_BBL_CR_D0   0x00000088

Chunk n data register D[63:0]: used to write to and read from the L2.

Parameters

ECX	MSR_P6_BBL_CR_Dn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);
AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);

Note

MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM. MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM. MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.

#define MSR_P6_BBL_CR_D1   0x00000089

Chunk n data register D[63:0]: used to write to and read from the L2.

Parameters

ECX	MSR_P6_BBL_CR_Dn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);
AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);

Note

MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM. MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM. MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.

#define MSR_P6_BBL_CR_D2   0x0000008A

Chunk n data register D[63:0]: used to write to and read from the L2.

Parameters

ECX	MSR_P6_BBL_CR_Dn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);
AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);

Note

MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM. MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM. MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.

#define MSR_P6_BBL_CR_DECC   0x00000118

Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.

Parameters

ECX	MSR_P6_BBL_CR_DECC (0x00000118)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);
AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);

Note

MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM.

#define MSR_P6_BBL_CR_TRIG   0x0000011A

Trigger register: used to initiate a cache configuration accesses access, Write only with Data = 0.

Parameters

ECX	MSR_P6_BBL_CR_TRIG (0x0000011A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);
AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);

Note

MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM.

#define MSR_P6_BIOS_SIGN   0x0000008B

BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to write to and read from the L2 depending on the usage model.

Parameters

ECX	MSR_P6_BIOS_SIGN (0x0000008B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);
AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);

Note

MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM.

#define MSR_P6_BIOS_UPDT_TRIG   0x00000079

BIOS Update Trigger Register.

Parameters

ECX	MSR_P6_BIOS_UPDT_TRIG (0x00000079)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);
AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);

Note

MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM.

#define MSR_P6_DEBUGCTLMSR   0x000001D9

Parameters

ECX	MSR_P6_DEBUGCTLMSR (0x000001D9)
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.

Example usage

MSR_P6_DEBUGCTLMSR_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);
AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);

Note

MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM.

#define MSR_P6_EBL_CR_POWERON   0x0000002A

Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.

Parameters

ECX	MSR_P6_EBL_CR_POWERON (0x0000002A)
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.

Example usage

MSR_P6_EBL_CR_POWERON_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);
AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);

Note

MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM.

#define MSR_P6_IA32_PLATFORM_ID   0x00000017

Platform ID (R) The operating system can use this MSR to determine "slot" information for the processor and the proper microcode update to load.

Parameters

ECX	MSR_P6_IA32_PLATFORM_ID (0x00000017)
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.

Example usage

MSR_P6_IA32_PLATFORM_ID_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);

Note

MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.

#define MSR_P6_LASTBRANCHFROMIP   0x000001DB

Parameters

ECX	MSR_P6_LASTBRANCHFROMIP (0x000001DB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);
AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);

Note

MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM.

#define MSR_P6_LASTBRANCHTOIP   0x000001DC

Parameters

ECX	MSR_P6_LASTBRANCHTOIP (0x000001DC)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);
AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);

Note

MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM.

#define MSR_P6_LASTINTFROMIP   0x000001DD

Parameters

ECX	MSR_P6_LASTINTFROMIP (0x000001DD)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);
AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);

Note

MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM.

#define MSR_P6_LASTINTTOIP   0x000001DE

Parameters

ECX	MSR_P6_LASTINTTOIP (0x000001DE)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);
AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);

Note

MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM.

#define MSR_P6_MC0_ADDR   0x00000402

MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.

Parameters

ECX	MSR_P6_MC0_ADDR (0x00000402)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);
AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);

Note

MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM. MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM. MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM. MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM. MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.

#define MSR_P6_MC0_CTL   0x00000400

Parameters

ECX	MSR_P6_MC0_CTL (0x00000400)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);
AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);

Note

MSR_P6_MC0_CTL is defined as MC0_CTL in SDM. MSR_P6_MC1_CTL is defined as MC1_CTL in SDM. MSR_P6_MC2_CTL is defined as MC2_CTL in SDM. MSR_P6_MC3_CTL is defined as MC3_CTL in SDM. MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.

#define MSR_P6_MC0_MISC   0x00000403

Defined in MCA architecture but not implemented in the P6 family processors.

Parameters

ECX	MSR_P6_MC0_MISC (0x00000403)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);
AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);

Note

MSR_P6_MC0_MISC is defined as MC0_MISC in SDM. MSR_P6_MC1_MISC is defined as MC1_MISC in SDM. MSR_P6_MC2_MISC is defined as MC2_MISC in SDM. MSR_P6_MC3_MISC is defined as MC3_MISC in SDM. MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.

#define MSR_P6_MC0_STATUS   0x00000401

Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS, except bits 0, 4, 57, and 61 are hardcoded to 1.

Parameters

ECX	MSR_P6_MCn_STATUS
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_MC_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_MC_STATUS_REGISTER.

Example usage

MSR_P6_MC_STATUS_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);
AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);

Note

MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM. MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM. MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM. MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM. MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.

#define MSR_P6_MC1_ADDR   0x00000406

MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.

Parameters

ECX	MSR_P6_MC0_ADDR (0x00000402)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);
AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);

Note

MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM. MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM. MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM. MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM. MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.

#define MSR_P6_MC1_CTL   0x00000404

Parameters

ECX	MSR_P6_MC0_CTL (0x00000400)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);
AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);

Note

MSR_P6_MC0_CTL is defined as MC0_CTL in SDM. MSR_P6_MC1_CTL is defined as MC1_CTL in SDM. MSR_P6_MC2_CTL is defined as MC2_CTL in SDM. MSR_P6_MC3_CTL is defined as MC3_CTL in SDM. MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.

#define MSR_P6_MC1_MISC   0x00000407

Defined in MCA architecture but not implemented in the P6 family processors.

Parameters

ECX	MSR_P6_MC0_MISC (0x00000403)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);
AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);

Note

MSR_P6_MC0_MISC is defined as MC0_MISC in SDM. MSR_P6_MC1_MISC is defined as MC1_MISC in SDM. MSR_P6_MC2_MISC is defined as MC2_MISC in SDM. MSR_P6_MC3_MISC is defined as MC3_MISC in SDM. MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.

#define MSR_P6_MC1_STATUS   0x00000405

Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS, except bits 0, 4, 57, and 61 are hardcoded to 1.

Parameters

ECX	MSR_P6_MCn_STATUS
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_MC_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_MC_STATUS_REGISTER.

Example usage

MSR_P6_MC_STATUS_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);
AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);

Note

MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM. MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM. MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM. MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM. MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.

#define MSR_P6_MC2_ADDR   0x0000040A

MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.

Parameters

ECX	MSR_P6_MC0_ADDR (0x00000402)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);
AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);

Note

MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM. MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM. MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM. MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM. MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.

#define MSR_P6_MC2_CTL   0x00000408

Parameters

ECX	MSR_P6_MC0_CTL (0x00000400)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);
AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);

Note

MSR_P6_MC0_CTL is defined as MC0_CTL in SDM. MSR_P6_MC1_CTL is defined as MC1_CTL in SDM. MSR_P6_MC2_CTL is defined as MC2_CTL in SDM. MSR_P6_MC3_CTL is defined as MC3_CTL in SDM. MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.

#define MSR_P6_MC2_MISC   0x0000040B

Defined in MCA architecture but not implemented in the P6 family processors.

Parameters

ECX	MSR_P6_MC0_MISC (0x00000403)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);
AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);

Note

MSR_P6_MC0_MISC is defined as MC0_MISC in SDM. MSR_P6_MC1_MISC is defined as MC1_MISC in SDM. MSR_P6_MC2_MISC is defined as MC2_MISC in SDM. MSR_P6_MC3_MISC is defined as MC3_MISC in SDM. MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.

#define MSR_P6_MC2_STATUS   0x00000409

Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS, except bits 0, 4, 57, and 61 are hardcoded to 1.

Parameters

ECX	MSR_P6_MCn_STATUS
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_MC_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_MC_STATUS_REGISTER.

Example usage

MSR_P6_MC_STATUS_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);
AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);

Note

MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM. MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM. MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM. MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM. MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.

#define MSR_P6_MC3_ADDR   0x00000412

MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.

Parameters

ECX	MSR_P6_MC0_ADDR (0x00000402)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);
AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);

Note

MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM. MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM. MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM. MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM. MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.

#define MSR_P6_MC3_CTL   0x00000410

Parameters

ECX	MSR_P6_MC0_CTL (0x00000400)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);
AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);

Note

MSR_P6_MC0_CTL is defined as MC0_CTL in SDM. MSR_P6_MC1_CTL is defined as MC1_CTL in SDM. MSR_P6_MC2_CTL is defined as MC2_CTL in SDM. MSR_P6_MC3_CTL is defined as MC3_CTL in SDM. MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.

#define MSR_P6_MC3_MISC   0x00000413

Defined in MCA architecture but not implemented in the P6 family processors.

Parameters

ECX	MSR_P6_MC0_MISC (0x00000403)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);
AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);

Note

MSR_P6_MC0_MISC is defined as MC0_MISC in SDM. MSR_P6_MC1_MISC is defined as MC1_MISC in SDM. MSR_P6_MC2_MISC is defined as MC2_MISC in SDM. MSR_P6_MC3_MISC is defined as MC3_MISC in SDM. MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.

#define MSR_P6_MC3_STATUS   0x00000411

Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS, except bits 0, 4, 57, and 61 are hardcoded to 1.

Parameters

ECX	MSR_P6_MCn_STATUS
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_MC_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_MC_STATUS_REGISTER.

Example usage

MSR_P6_MC_STATUS_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);
AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);

Note

MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM. MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM. MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM. MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM. MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.

#define MSR_P6_MC4_ADDR   0x0000040E

MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.

Parameters

ECX	MSR_P6_MC0_ADDR (0x00000402)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);
AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);

Note

MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM. MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM. MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM. MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM. MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.

#define MSR_P6_MC4_CTL   0x0000040C

Parameters

ECX	MSR_P6_MC0_CTL (0x00000400)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);
AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);

Note

MSR_P6_MC0_CTL is defined as MC0_CTL in SDM. MSR_P6_MC1_CTL is defined as MC1_CTL in SDM. MSR_P6_MC2_CTL is defined as MC2_CTL in SDM. MSR_P6_MC3_CTL is defined as MC3_CTL in SDM. MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.

#define MSR_P6_MC4_MISC   0x0000040F

Defined in MCA architecture but not implemented in the P6 family processors.

Parameters

ECX	MSR_P6_MC0_MISC (0x00000403)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);
AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);

Note

MSR_P6_MC0_MISC is defined as MC0_MISC in SDM. MSR_P6_MC1_MISC is defined as MC1_MISC in SDM. MSR_P6_MC2_MISC is defined as MC2_MISC in SDM. MSR_P6_MC3_MISC is defined as MC3_MISC in SDM. MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.

#define MSR_P6_MC4_STATUS   0x0000040D

Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS, except bits 0, 4, 57, and 61 are hardcoded to 1.

Parameters

ECX	MSR_P6_MCn_STATUS
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_MC_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_MC_STATUS_REGISTER.

Example usage

MSR_P6_MC_STATUS_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);
AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);

Note

MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM. MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM. MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM. MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM. MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.

#define MSR_P6_MCG_CAP   0x00000179

Parameters

ECX	MSR_P6_MCG_CAP (0x00000179)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);
AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);

Note

MSR_P6_MCG_CAP is defined as MCG_CAP in SDM.

#define MSR_P6_MCG_CTL   0x0000017B

Parameters

ECX	MSR_P6_MCG_CTL (0x0000017B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);
AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);

Note

MSR_P6_MCG_CTL is defined as MCG_CTL in SDM.

#define MSR_P6_MCG_STATUS   0x0000017A

Parameters

ECX	MSR_P6_MCG_STATUS (0x0000017A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);
AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);

Note

MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM.

#define MSR_P6_MTRRCAP   0x000000FE

Parameters

ECX	MSR_P6_MTRRCAP (0x000000FE)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);
AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);

Note

MSR_P6_MTRRCAP is defined as MTRRCAP in SDM.

#define MSR_P6_MTRRDEFTYPE   0x000002FF

Parameters

ECX	MSR_P6_MTRRDEFTYPE (0x000002FF)
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.

Example usage

MSR_P6_MTRRDEFTYPE_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);
AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);

Note

MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM.

#define MSR_P6_MTRRFIX16K_80000   0x00000258

Parameters

ECX	MSR_P6_MTRRFIX16K_80000 (0x00000258)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);
AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);

Note

MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.

#define MSR_P6_MTRRFIX16K_A0000   0x00000259

Parameters

ECX	MSR_P6_MTRRFIX16K_A0000 (0x00000259)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);
AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);

Note

MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.

#define MSR_P6_MTRRFIX4K_C0000   0x00000268

Parameters

ECX	MSR_P6_MTRRFIX4K_C0000 (0x00000268)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);

Note

MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.

#define MSR_P6_MTRRFIX4K_C8000   0x00000269

Parameters

ECX	MSR_P6_MTRRFIX4K_C8000 (0x00000269)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);

Note

MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.

#define MSR_P6_MTRRFIX4K_D0000   0x0000026A

Parameters

ECX	MSR_P6_MTRRFIX4K_D0000 (0x0000026A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);

Note

MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.

#define MSR_P6_MTRRFIX4K_D8000   0x0000026B

Parameters

ECX	MSR_P6_MTRRFIX4K_D8000 (0x0000026B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);

Note

MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.

#define MSR_P6_MTRRFIX4K_E0000   0x0000026C

Parameters

ECX	MSR_P6_MTRRFIX4K_E0000 (0x0000026C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);

Note

MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.

#define MSR_P6_MTRRFIX4K_E8000   0x0000026D

Parameters

ECX	MSR_P6_MTRRFIX4K_E8000 (0x0000026D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);

Note

MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.

#define MSR_P6_MTRRFIX4K_F0000   0x0000026E

Parameters

ECX	MSR_P6_MTRRFIX4K_F0000 (0x0000026E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);

Note

MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.

#define MSR_P6_MTRRFIX4K_F8000   0x0000026F

Parameters

ECX	MSR_P6_MTRRFIX4K_F8000 (0x0000026F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);
AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);

Note

MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.

#define MSR_P6_MTRRFIX64K_00000   0x00000250

Parameters

ECX	MSR_P6_MTRRFIX64K_00000 (0x00000250)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);
AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);

Note

MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.

#define MSR_P6_MTRRPHYSBASE0   0x00000200

Parameters

ECX	MSR_P6_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);

Note

MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_P6_MTRRPHYSBASE1   0x00000202

Parameters

ECX	MSR_P6_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);

Note

MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_P6_MTRRPHYSBASE2   0x00000204

Parameters

ECX	MSR_P6_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);

Note

MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_P6_MTRRPHYSBASE3   0x00000206

Parameters

ECX	MSR_P6_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);

Note

MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_P6_MTRRPHYSBASE4   0x00000208

Parameters

ECX	MSR_P6_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);

Note

MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_P6_MTRRPHYSBASE5   0x0000020A

Parameters

ECX	MSR_P6_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);

Note

MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_P6_MTRRPHYSBASE6   0x0000020C

Parameters

ECX	MSR_P6_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);

Note

MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_P6_MTRRPHYSBASE7   0x0000020E

Parameters

ECX	MSR_P6_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);

Note

MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_P6_MTRRPHYSMASK0   0x00000201

Parameters

ECX	MSR_P6_MTRRPHYSMASKn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);

Note

MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_P6_MTRRPHYSMASK1   0x00000203

Parameters

ECX	MSR_P6_MTRRPHYSMASKn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);

Note

MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_P6_MTRRPHYSMASK2   0x00000205

Parameters

ECX	MSR_P6_MTRRPHYSMASKn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);

Note

MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_P6_MTRRPHYSMASK3   0x00000207

Parameters

ECX	MSR_P6_MTRRPHYSMASKn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);

Note

MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_P6_MTRRPHYSMASK4   0x00000209

Parameters

ECX	MSR_P6_MTRRPHYSMASKn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);

Note

MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_P6_MTRRPHYSMASK5   0x0000020B

Parameters

ECX	MSR_P6_MTRRPHYSMASKn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);

Note

MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_P6_MTRRPHYSMASK6   0x0000020D

Parameters

ECX	MSR_P6_MTRRPHYSMASKn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);

Note

MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_P6_MTRRPHYSMASK7   0x0000020F

Parameters

ECX	MSR_P6_MTRRPHYSMASKn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);

Note

MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_P6_P5_MC_ADDR   0x00000000

See Section 2.22, "MSRs in Pentium Processors.".

Parameters

ECX	MSR_P6_P5_MC_ADDR (0x00000000)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);
AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);

Note

MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.

#define MSR_P6_P5_MC_TYPE   0x00000001

See Section 2.22, "MSRs in Pentium Processors.".

Parameters

ECX	MSR_P6_P5_MC_TYPE (0x00000001)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);
AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);

Note

MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.

#define MSR_P6_PERFCTR0   0x000000C1

Parameters

ECX	MSR_P6_PERFCTR0 (0x000000C1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);
AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);

Note

MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM. MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.

#define MSR_P6_PERFCTR1   0x000000C2

Parameters

ECX	MSR_P6_PERFCTR0 (0x000000C1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);
AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);

Note

MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM. MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.

#define MSR_P6_PERFEVTSEL0   0x00000186

Parameters

ECX	MSR_P6_PERFEVTSELn
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_PERFEVTSEL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_PERFEVTSEL_REGISTER.

Example usage

MSR_P6_PERFEVTSEL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);
AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);

Note

MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM. MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM.

#define MSR_P6_PERFEVTSEL1   0x00000187

Parameters

ECX	MSR_P6_PERFEVTSELn
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_PERFEVTSEL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_PERFEVTSEL_REGISTER.

Example usage

MSR_P6_PERFEVTSEL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);
AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);

Note

MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM. MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM.

#define MSR_P6_SYSENTER_CS_MSR   0x00000174

CS register target for CPL 0 code.

Parameters

ECX	MSR_P6_SYSENTER_CS_MSR (0x00000174)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);
AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);

Note

MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM.

#define MSR_P6_SYSENTER_EIP_MSR   0x00000176

CPL 0 code entry point.

Parameters

ECX	MSR_P6_SYSENTER_EIP_MSR (0x00000176)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);
AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);

Note

MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM.

#define MSR_P6_SYSENTER_ESP_MSR   0x00000175

Stack pointer for CPL 0 stack.

Parameters

ECX	MSR_P6_SYSENTER_ESP_MSR (0x00000175)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);
AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);

Note

MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM.

#define MSR_P6_TEST_CTL   0x00000033

Test Control Register.

Parameters

ECX	MSR_P6_TEST_CTL (0x00000033)
EAX	Lower 32-bits of MSR value. Described by the type MSR_P6_TEST_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_P6_TEST_CTL_REGISTER.

Example usage

MSR_P6_TEST_CTL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);
AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);

Note

MSR_P6_TEST_CTL is defined as TEST_CTL in SDM.

#define MSR_P6_TSC   0x00000010

See Section 17.17, "Time-Stamp Counter.".

Parameters

ECX	MSR_P6_TSC (0x00000010)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_P6_TSC);
AsmWriteMsr64 (MSR_P6_TSC, Msr);

Note

MSR_P6_TSC is defined as TSC in SDM.