MSR_P6_PERFEVTSEL_REGISTER Union Reference

Data Fields
struct {
UINT32   EventSelect:8
UINT32   UMASK:8
UINT32   USR:1
UINT32   OS:1
UINT32   E:1
UINT32   PC:1
UINT32   INT:1
UINT32   Reserved1:1
UINT32   EN:1
UINT32   INV:1
UINT32   CMASK:8
UINT32   Reserved2:32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR indexes MSR_P6_PERFEVTSEL0 and MSR_P6_PERFEVTSEL1.

Field Documentation

struct { ... } MSR_P6_PERFEVTSEL_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_PERFEVTSEL_REGISTER::CMASK

[Bits 31:24] CMASK (Counter Mask).

UINT32 MSR_P6_PERFEVTSEL_REGISTER::E

[Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::EN

[Bit 22] ENABLE Enables the counting of performance events in both counters 1 = Enable 0 = Disable.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::EventSelect

[Bits 7:0] Event Select Refer to Performance Counter section for a list of event encodings.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::INT

[Bit 20] INT Enables the signaling of counter overflow via input to APIC 1 = Enable 0 = Disable.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::INV

[Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0 = Non-Inverted.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::OS

[Bit 17] OS Controls the counting of events at Privilege level of 0.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::PC

[Bit 19] PC Enabled the signaling of performance counter overflow via BP0 pin.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::Reserved1

UINT32 MSR_P6_PERFEVTSEL_REGISTER::Reserved2

UINT32 MSR_P6_PERFEVTSEL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_P6_PERFEVTSEL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_P6_PERFEVTSEL_REGISTER::UMASK

[Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable all count options.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::USR

[Bit 16] USER Controls the counting of events at Privilege levels of 1, 2, and 3.