MSR_P6_BBL_CR_CTL_REGISTER Union Reference

Data Fields
struct {
UINT32   L2Command:5
UINT32   StateToL2:2
UINT32   Reserved:1
UINT32   WayToL2:2
UINT32   Way:2
UINT32   MESI:2
UINT32   StateFromL2:2
UINT32   Reserved2:1
UINT32   L2Hit:1
UINT32   Reserved3:1
UINT32   UserEcc:2
UINT32   ProcessorNumber:1
UINT32   Reserved4:10
UINT32   Reserved5:32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_P6_BBL_CR_CTL

Field Documentation

struct { ... } MSR_P6_BBL_CR_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::L2Command

[Bits 4:0] L2 Command Data Read w/ LRU update (RLU) Tag Read w/ Data Read (TRR) Tag Inquire (TI) L2 Control Register Read (CR) L2 Control Register Write (CW) Tag Write w/ Data Read (TWR) Tag Write w/ Data Write (TWW) Tag Write (TW).

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::L2Hit

[Bit 17] L2 Hit.

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::MESI

[Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::ProcessorNumber

[Bit 21] Processor number Disable = 1 Enable = 0 Reserved.

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::Reserved

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::Reserved2

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::Reserved3

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::Reserved4

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::Reserved5

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::StateFromL2

[Bits 15:14] State from L2.

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::StateToL2

[Bits 6:5] State to L2

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_P6_BBL_CR_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::UserEcc

[Bits 20:19] User supplied ECC.

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::Way

[Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::WayToL2

[Bits 9:8] Way to L2.