MSR_P6_EBL_CR_POWERON_REGISTER Union Reference

Data Fields
struct {
UINT32   Reserved1:1
UINT32   DataErrorCheckingEnable:1
UINT32   ResponseErrorCheckingEnable:1
UINT32   AERR_DriveEnable:1
UINT32   BERR_Enable:1
UINT32   Reserved2:1
UINT32   BERR_DriverEnable:1
UINT32   BINIT_DriverEnable:1
UINT32   OutputTriStateEnable:1
UINT32   ExecuteBIST:1
UINT32   AERR_ObservationEnabled:1
UINT32   Reserved3:1
UINT32   BINIT_ObservationEnabled:1
UINT32   InOrderQueueDepth:1
UINT32   ResetVector:1
UINT32   FRCModeEnable:1
UINT32   APICClusterID:2
UINT32   SystemBusFrequency:2
UINT32   SymmetricArbitrationID:2
UINT32   ClockFrequencyRatio:4
UINT32   LowPowerModeEnable:1
UINT32   ClockFrequencyRatio1:1
UINT32   Reserved4:4
UINT32   Reserved5:32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_P6_EBL_CR_POWERON

Field Documentation

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::AERR_DriveEnable

[Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::AERR_ObservationEnabled

[Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::APICClusterID

[Bits 17:16] APIC Cluster ID (R).

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::BERR_DriverEnable

[Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::BERR_Enable

[Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::BINIT_DriverEnable

[Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::BINIT_ObservationEnabled

[Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.

struct { ... } MSR_P6_EBL_CR_POWERON_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::ClockFrequencyRatio

[Bits 25:22] Clock Frequency Ratio (R).

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::ClockFrequencyRatio1

[Bit 27] Clock Frequency Ratio.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::DataErrorCheckingEnable

[Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::ExecuteBIST

[Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::FRCModeEnable

[Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::InOrderQueueDepth

[Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::LowPowerModeEnable

[Bit 26] Low Power Mode Enable (R/W).

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::OutputTriStateEnable

[Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::Reserved1

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::Reserved2

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::Reserved3

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::Reserved4

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::Reserved5

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::ResetVector

[Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::ResponseErrorCheckingEnable

[Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::SymmetricArbitrationID

[Bits 21:20] Symmetric Arbitration ID (R).

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::SystemBusFrequency

[Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 = 133MHz 11 = Reserved.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_P6_EBL_CR_POWERON_REGISTER::Uint64

All bit fields as a 64-bit value