Data Structures
union	MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER

union	MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER

union	MSR_PENTIUM_M_THERM2_CTL_REGISTER

union	MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER

Macros
#define	IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel)

#define	MSR_PENTIUM_M_P5_MC_ADDR 0x00000000

#define	MSR_PENTIUM_M_P5_MC_TYPE 0x00000001

#define	MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A

#define	MSR_PENTIUM_M_BBL_CR_CTL 0x00000119

#define	MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E

#define	MSR_PENTIUM_M_THERM2_CTL 0x0000019D

#define	MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0

#define	MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9

#define	MSR_PENTIUM_M_DEBUGCTLB 0x000001D9

#define	MSR_PENTIUM_M_LER_TO_LIP 0x000001DD

#define	MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE

#define	MSR_PENTIUM_M_MC4_CTL 0x0000040C

#define	MSR_PENTIUM_M_MC4_STATUS 0x0000040D

#define	MSR_PENTIUM_M_MC4_ADDR 0x0000040E

#define	MSR_PENTIUM_M_MC3_CTL 0x00000410

#define	MSR_PENTIUM_M_MC3_STATUS 0x00000411

#define	MSR_PENTIUM_M_MC3_ADDR 0x00000412


#define	MSR_PENTIUM_M_LASTBRANCH_0 0x00000040

#define	MSR_PENTIUM_M_LASTBRANCH_1 0x00000041

#define	MSR_PENTIUM_M_LASTBRANCH_2 0x00000042

#define	MSR_PENTIUM_M_LASTBRANCH_3 0x00000043

#define	MSR_PENTIUM_M_LASTBRANCH_4 0x00000044

#define	MSR_PENTIUM_M_LASTBRANCH_5 0x00000045

#define	MSR_PENTIUM_M_LASTBRANCH_6 0x00000046

#define	MSR_PENTIUM_M_LASTBRANCH_7 0x00000047

Detailed Description

MSR Definitions for Pentium M Processors.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_PENTIUM_M_PROCESSOR	(	DisplayFamily,
		DisplayModel
	)

Value:

(DisplayFamily == 0x06 && \
   ( \
    DisplayModel == 0x0D \
    ) \
   )

Is Pentium M Processors?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119

Reserved.

Parameters

ECX	MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);

Note: MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.

#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E

Parameters

ECX	MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)
EAX	Lower 32-bits of MSR value. Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.

Example usage

MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);

Note: MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.

#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9

Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section. See Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".

Parameters

ECX	MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);

Note: MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.

#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A

Processor Hard Power-On Configuration (R/W) Enables and disables processor features. (R) Indicates current processor configuration.

Parameters

ECX	MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)
EAX	Lower 32-bits of MSR value. Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.

Example usage

MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);

Note: MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.

#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0

Enable Miscellaneous Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.

Parameters

ECX	MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.

Example usage

MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);

Note: MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.

#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040

Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)".

Parameters

ECX	MSR_PENTIUM_M_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);

Note: MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041

Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)".

Parameters

ECX	MSR_PENTIUM_M_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);

Note: MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042

Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)".

Parameters

ECX	MSR_PENTIUM_M_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);

Note: MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043

Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)".

Parameters

ECX	MSR_PENTIUM_M_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);

Note: MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044

Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)".

Parameters

ECX	MSR_PENTIUM_M_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);

Note: MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045

Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)".

Parameters

ECX	MSR_PENTIUM_M_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);

Note: MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046

Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)".

Parameters

ECX	MSR_PENTIUM_M_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);

Note: MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047

Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)".

Parameters

ECX	MSR_PENTIUM_M_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);

Note: MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9

Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points to the MSR containing the most recent branch record. See also: - MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)".

Parameters

ECX	MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);

Note: MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.

#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE

Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".

Parameters

ECX	MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);

Note: MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.

#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD

Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".

Parameters

ECX	MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);

Note: MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.

#define MSR_PENTIUM_M_MC3_ADDR 0x00000412

See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

Parameters

ECX	MSR_PENTIUM_M_MC3_ADDR (0x00000412)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);

Note: MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.

#define MSR_PENTIUM_M_MC3_CTL 0x00000410

See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".

Parameters

ECX	MSR_PENTIUM_M_MC3_CTL (0x00000410)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);

Note: MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.

#define MSR_PENTIUM_M_MC3_STATUS 0x00000411

See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".

Parameters

ECX	MSR_PENTIUM_M_MC3_STATUS (0x00000411)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);

Note: MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.

#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E

See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

Parameters

ECX	MSR_PENTIUM_M_MC4_ADDR (0x0000040E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);

Note: MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.

#define MSR_PENTIUM_M_MC4_CTL 0x0000040C

See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".

Parameters

ECX	MSR_PENTIUM_M_MC4_CTL (0x0000040C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);

Note: MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.

#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D

See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".

Parameters

ECX	MSR_PENTIUM_M_MC4_STATUS (0x0000040D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);

Note: MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.

#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000

See Section 2.22, "MSRs in Pentium Processors.".

Parameters

ECX	MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);

Note: MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.

#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001

See Section 2.22, "MSRs in Pentium Processors.".

Parameters

ECX	MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);

Note: MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.

#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D

Parameters

ECX	MSR_PENTIUM_M_THERM2_CTL (0x0000019D)
EAX	Lower 32-bits of MSR value. Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.

Example usage

MSR_PENTIUM_M_THERM2_CTL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);

Note: MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.

Data Structures

Macros

Detailed Description

Macro Definition Documentation