Data Fields
struct {
UINT32 Reserved1:1

UINT32 DataErrorCheckingEnable:1

UINT32 ResponseErrorCheckingEnable:1

UINT32 MCERR_DriveEnable:1

UINT32 AddressParityEnable:1

UINT32 Reserved2:2

UINT32 BINIT_DriverEnable:1

UINT32 OutputTriStateEnable:1

UINT32 ExecuteBIST:1

UINT32 MCERR_ObservationEnabled:1

UINT32 Reserved3:1

UINT32 BINIT_ObservationEnabled:1

UINT32 Reserved4:1

UINT32 ResetVector:1

UINT32 Reserved5:1

UINT32 APICClusterID:2

UINT32 SystemBusFrequency:1

UINT32 Reserved6:1

UINT32 SymmetricArbitrationID:2

UINT32 ClockFrequencyRatio:5

UINT32 Reserved7:5

UINT32 Reserved8:32

}	Bits

UINT32	Uint32

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_PENTIUM_M_EBL_CR_POWERON

Field Documentation

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::AddressParityEnable

[Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::APICClusterID

[Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::BINIT_DriverEnable

[Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::BINIT_ObservationEnabled

[Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled Always 0 on the Pentium M processor.

struct { ... } MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::ClockFrequencyRatio

[Bits 26:22] Clock Frequency Ratio (R/O).

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::DataErrorCheckingEnable

[Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::ExecuteBIST

[Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::MCERR_DriveEnable

[Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::MCERR_ObservationEnabled

[Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::OutputTriStateEnable

[Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Reserved1

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Reserved2

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Reserved3

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Reserved4

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Reserved5

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Reserved6

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Reserved7

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Reserved8

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::ResetVector

[Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::ResponseErrorCheckingEnable

[Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::SymmetricArbitrationID

[Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::SystemBusFrequency

[Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Uint64

All bit fields as a 64-bit value