MSR information returned for MSR index MSR_PENTIUM_M_IA32_MISC_ENABLE
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit |
[Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting this bit enables the thermal control circuit (TCC) portion of the Intel Thermal Monitor feature. This allows processor clocks to be automatically modulated based on the processor's thermal sensor operation. 0 = Disabled (default). The automatic thermal control circuit enable bit determines if the thermal control circuit (TCC) will be activated when the processor's internal thermal sensor determines the processor is about to exceed its maximum operating temperature. When the TCC is activated and TM1 is enabled, the processors clocks will be forced to a 50% duty cycle. BIOS must enable this feature. The bit should not be confused with the on-demand thermal control circuit enable bit.
| struct { ... } MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Bits |
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::BTS |
[Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't support branch trace storage (BTS) 0 = BTS is supported
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::EIST |
[Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 = Enhanced Intel SpeedStep Technology enabled. On the Pentium M processor, this bit may be configured to be read-only.
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::FERR |
[Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the processor to indicate a pending break event within the processor 0 = Indicates compatible FERR# signaling behavior This bit must be set to 1 to support XAPIC interrupt model usage. Branch Trace Storage Unavailable (RO) 1 = Processor doesn't support branch trace storage (BTS) 0 = BTS is supported
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::PEBS |
[Bit 12] Processor Event Based Sampling Unavailable (RO) 1 = Processor does not support processor event based sampling (PEBS); 0 = PEBS is supported. The Pentium M processor does not support PEBS.
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring |
[Bit 7] Performance Monitoring Available (R) 1 = Performance monitoring enabled 0 = Performance monitoring disabled.
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved1 |
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved2 |
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved3 |
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved5 |
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved6 |
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved7 |
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved8 |
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Uint32 |
All bit fields as a 32-bit value
| UINT64 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Uint64 |
All bit fields as a 64-bit value
| UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable |
[Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are disabled. xTPR messages are optional messages that allow the processor to inform the chipset of its priority. The default is processor specific.
1.8.6 
