Data Structures
union	MSR_NEHALEM_PLATFORM_ID_REGISTER

union	MSR_NEHALEM_SMI_COUNT_REGISTER

union	MSR_NEHALEM_PLATFORM_INFO_REGISTER

union	MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER

union	MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER

union	MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER

union	MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER

union	MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER

union	MSR_NEHALEM_MISC_PWR_MGMT_REGISTER

union	MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER

union	MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER

union	MSR_NEHALEM_LBR_SELECT_REGISTER

union	MSR_NEHALEM_POWER_CTL_REGISTER

union	MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER

union	MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER

union	MSR_NEHALEM_PEBS_ENABLE_REGISTER

union	MSR_NEHALEM_PEBS_LD_LAT_REGISTER

union	MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER

Macros
#define	IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel)

#define	MSR_NEHALEM_PLATFORM_ID 0x00000017

#define	MSR_NEHALEM_SMI_COUNT 0x00000034

#define	MSR_NEHALEM_PLATFORM_INFO 0x000000CE

#define	MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2

#define	MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4

#define	MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0

#define	MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2

#define	MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4

#define	MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6

#define	MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA

#define	MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC

#define	MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD

#define	MSR_NEHALEM_LBR_SELECT 0x000001C8

#define	MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9

#define	MSR_NEHALEM_LER_FROM_LIP 0x000001DD

#define	MSR_NEHALEM_LER_TO_LIP 0x000001DE

#define	MSR_NEHALEM_POWER_CTL 0x000001FC

#define	MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E

#define	MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390

#define	MSR_NEHALEM_PEBS_ENABLE 0x000003F1

#define	MSR_NEHALEM_PEBS_LD_LAT 0x000003F6

#define	MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8

#define	MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9

#define	MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA

#define	MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC

#define	MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD

#define	MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301

#define	MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391

#define	MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392

#define	MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393

#define	MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394

#define	MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395

#define	MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396

#define	MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394

#define	MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395

#define	MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00

#define	MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01

#define	MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02

#define	MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10

#define	MSR_NEHALEM_U_PMON_CTR 0x00000C11

#define	MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20

#define	MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21

#define	MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22

#define	MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30

#define	MSR_NEHALEM_B0_PMON_CTR0 0x00000C31

#define	MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32

#define	MSR_NEHALEM_B0_PMON_CTR1 0x00000C33

#define	MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34

#define	MSR_NEHALEM_B0_PMON_CTR2 0x00000C35

#define	MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36

#define	MSR_NEHALEM_B0_PMON_CTR3 0x00000C37

#define	MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40

#define	MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41

#define	MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42

#define	MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50

#define	MSR_NEHALEM_S0_PMON_CTR0 0x00000C51

#define	MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52

#define	MSR_NEHALEM_S0_PMON_CTR1 0x00000C53

#define	MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54

#define	MSR_NEHALEM_S0_PMON_CTR2 0x00000C55

#define	MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56

#define	MSR_NEHALEM_S0_PMON_CTR3 0x00000C57

#define	MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60

#define	MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61

#define	MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62

#define	MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70

#define	MSR_NEHALEM_B1_PMON_CTR0 0x00000C71

#define	MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72

#define	MSR_NEHALEM_B1_PMON_CTR1 0x00000C73

#define	MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74

#define	MSR_NEHALEM_B1_PMON_CTR2 0x00000C75

#define	MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76

#define	MSR_NEHALEM_B1_PMON_CTR3 0x00000C77

#define	MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80

#define	MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81

#define	MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82

#define	MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90

#define	MSR_NEHALEM_W_PMON_CTR0 0x00000C91

#define	MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92

#define	MSR_NEHALEM_W_PMON_CTR1 0x00000C93

#define	MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94

#define	MSR_NEHALEM_W_PMON_CTR2 0x00000C95

#define	MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96

#define	MSR_NEHALEM_W_PMON_CTR3 0x00000C97

#define	MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0

#define	MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1

#define	MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2

#define	MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4

#define	MSR_NEHALEM_M0_PMON_DSP 0x00000CA5

#define	MSR_NEHALEM_M0_PMON_ISS 0x00000CA6

#define	MSR_NEHALEM_M0_PMON_MAP 0x00000CA7

#define	MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8

#define	MSR_NEHALEM_M0_PMON_PGT 0x00000CA9

#define	MSR_NEHALEM_M0_PMON_PLD 0x00000CAA

#define	MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB

#define	MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0

#define	MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1

#define	MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2

#define	MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3

#define	MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4

#define	MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5

#define	MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6

#define	MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7

#define	MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8

#define	MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9

#define	MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA

#define	MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB

#define	MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0

#define	MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1

#define	MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2

#define	MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0

#define	MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1

#define	MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2

#define	MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3

#define	MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4

#define	MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5

#define	MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6

#define	MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7

#define	MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0

#define	MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1

#define	MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2

#define	MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4

#define	MSR_NEHALEM_M1_PMON_DSP 0x00000CE5

#define	MSR_NEHALEM_M1_PMON_ISS 0x00000CE6

#define	MSR_NEHALEM_M1_PMON_MAP 0x00000CE7

#define	MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8

#define	MSR_NEHALEM_M1_PMON_PGT 0x00000CE9

#define	MSR_NEHALEM_M1_PMON_PLD 0x00000CEA

#define	MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB

#define	MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0

#define	MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1

#define	MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2

#define	MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3

#define	MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4

#define	MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5

#define	MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6

#define	MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7

#define	MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8

#define	MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9

#define	MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA

#define	MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB

#define	MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00

#define	MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01

#define	MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02

#define	MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10

#define	MSR_NEHALEM_C0_PMON_CTR0 0x00000D11

#define	MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12

#define	MSR_NEHALEM_C0_PMON_CTR1 0x00000D13

#define	MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14

#define	MSR_NEHALEM_C0_PMON_CTR2 0x00000D15

#define	MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16

#define	MSR_NEHALEM_C0_PMON_CTR3 0x00000D17

#define	MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18

#define	MSR_NEHALEM_C0_PMON_CTR4 0x00000D19

#define	MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A

#define	MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B

#define	MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20

#define	MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21

#define	MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22

#define	MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30

#define	MSR_NEHALEM_C4_PMON_CTR0 0x00000D31

#define	MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32

#define	MSR_NEHALEM_C4_PMON_CTR1 0x00000D33

#define	MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34

#define	MSR_NEHALEM_C4_PMON_CTR2 0x00000D35

#define	MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36

#define	MSR_NEHALEM_C4_PMON_CTR3 0x00000D37

#define	MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38

#define	MSR_NEHALEM_C4_PMON_CTR4 0x00000D39

#define	MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A

#define	MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B

#define	MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40

#define	MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41

#define	MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42

#define	MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50

#define	MSR_NEHALEM_C2_PMON_CTR0 0x00000D51

#define	MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52

#define	MSR_NEHALEM_C2_PMON_CTR1 0x00000D53

#define	MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54

#define	MSR_NEHALEM_C2_PMON_CTR2 0x00000D55

#define	MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56

#define	MSR_NEHALEM_C2_PMON_CTR3 0x00000D57

#define	MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58

#define	MSR_NEHALEM_C2_PMON_CTR4 0x00000D59

#define	MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A

#define	MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B

#define	MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60

#define	MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61

#define	MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62

#define	MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70

#define	MSR_NEHALEM_C6_PMON_CTR0 0x00000D71

#define	MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72

#define	MSR_NEHALEM_C6_PMON_CTR1 0x00000D73

#define	MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74

#define	MSR_NEHALEM_C6_PMON_CTR2 0x00000D75

#define	MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76

#define	MSR_NEHALEM_C6_PMON_CTR3 0x00000D77

#define	MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78

#define	MSR_NEHALEM_C6_PMON_CTR4 0x00000D79

#define	MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A

#define	MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B

#define	MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80

#define	MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81

#define	MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82

#define	MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90

#define	MSR_NEHALEM_C1_PMON_CTR0 0x00000D91

#define	MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92

#define	MSR_NEHALEM_C1_PMON_CTR1 0x00000D93

#define	MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94

#define	MSR_NEHALEM_C1_PMON_CTR2 0x00000D95

#define	MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96

#define	MSR_NEHALEM_C1_PMON_CTR3 0x00000D97

#define	MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98

#define	MSR_NEHALEM_C1_PMON_CTR4 0x00000D99

#define	MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A

#define	MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B

#define	MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0

#define	MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1

#define	MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2

#define	MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0

#define	MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1

#define	MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2

#define	MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3

#define	MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4

#define	MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5

#define	MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6

#define	MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7

#define	MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8

#define	MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9

#define	MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA

#define	MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB

#define	MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0

#define	MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1

#define	MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2

#define	MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0

#define	MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1

#define	MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2

#define	MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3

#define	MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4

#define	MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5

#define	MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6

#define	MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7

#define	MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8

#define	MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9

#define	MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA

#define	MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB

#define	MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0

#define	MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1

#define	MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2

#define	MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0

#define	MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1

#define	MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2

#define	MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3

#define	MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4

#define	MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5

#define	MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6

#define	MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7

#define	MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8

#define	MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9

#define	MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA

#define	MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB

#define	MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00

#define	MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01

#define	MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02

#define	MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04

#define	MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05

#define	MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06

#define	MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07

#define	MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08

#define	MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09

#define	MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A

#define	MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B

#define	MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C

#define	MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D

#define	MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E

#define	MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F

#define	MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10

#define	MSR_NEHALEM_R0_PMON_CTR0 0x00000E11

#define	MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12

#define	MSR_NEHALEM_R0_PMON_CTR1 0x00000E13

#define	MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14

#define	MSR_NEHALEM_R0_PMON_CTR2 0x00000E15

#define	MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16

#define	MSR_NEHALEM_R0_PMON_CTR3 0x00000E17

#define	MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18

#define	MSR_NEHALEM_R0_PMON_CTR4 0x00000E19

#define	MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A

#define	MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B

#define	MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C

#define	MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D

#define	MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E

#define	MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F

#define	MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20

#define	MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21

#define	MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22

#define	MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24

#define	MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25

#define	MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26

#define	MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27

#define	MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28

#define	MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29

#define	MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A

#define	MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B

#define	MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C

#define	MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D

#define	MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E

#define	MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F

#define	MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30

#define	MSR_NEHALEM_R1_PMON_CTR8 0x00000E31

#define	MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32

#define	MSR_NEHALEM_R1_PMON_CTR9 0x00000E33

#define	MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34

#define	MSR_NEHALEM_R1_PMON_CTR10 0x00000E35

#define	MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36

#define	MSR_NEHALEM_R1_PMON_CTR11 0x00000E37

#define	MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38

#define	MSR_NEHALEM_R1_PMON_CTR12 0x00000E39

#define	MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A

#define	MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B

#define	MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C

#define	MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D

#define	MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E

#define	MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F

#define	MSR_NEHALEM_B0_PMON_MATCH 0x00000E45

#define	MSR_NEHALEM_B0_PMON_MASK 0x00000E46

#define	MSR_NEHALEM_S0_PMON_MATCH 0x00000E49

#define	MSR_NEHALEM_S0_PMON_MASK 0x00000E4A

#define	MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D

#define	MSR_NEHALEM_B1_PMON_MASK 0x00000E4E

#define	MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54

#define	MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55

#define	MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56

#define	MSR_NEHALEM_S1_PMON_MATCH 0x00000E59

#define	MSR_NEHALEM_S1_PMON_MASK 0x00000E5A

#define	MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C

#define	MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D

#define	MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E


#define	MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680

#define	MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681

#define	MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682

#define	MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683

#define	MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684

#define	MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685

#define	MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686

#define	MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687

#define	MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688

#define	MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689

#define	MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A

#define	MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B

#define	MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C

#define	MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D

#define	MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E

#define	MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F


#define	MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0

#define	MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1

#define	MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2

#define	MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3

#define	MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4

#define	MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5

#define	MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6

#define	MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7

#define	MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8

#define	MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9

#define	MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA

#define	MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB

#define	MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC

#define	MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD

#define	MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE

#define	MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF


#define	MSR_NEHALEM_UNCORE_PMC0 0x000003B0

#define	MSR_NEHALEM_UNCORE_PMC1 0x000003B1

#define	MSR_NEHALEM_UNCORE_PMC2 0x000003B2

#define	MSR_NEHALEM_UNCORE_PMC3 0x000003B3

#define	MSR_NEHALEM_UNCORE_PMC4 0x000003B4

#define	MSR_NEHALEM_UNCORE_PMC5 0x000003B5

#define	MSR_NEHALEM_UNCORE_PMC6 0x000003B6

#define	MSR_NEHALEM_UNCORE_PMC7 0x000003B7


#define	MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0

#define	MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1

#define	MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2

#define	MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3

#define	MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4

#define	MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5

#define	MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6

#define	MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7

Detailed Description

MSR Definitions for Intel processors based on the Nehalem microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_NEHALEM_PROCESSOR	(	DisplayFamily,
		DisplayModel
	)

Value:

(DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x1A || \
    DisplayModel == 0x1E || \
    DisplayModel == 0x1F || \
    DisplayModel == 0x2E    \
    )                       \
   )

Is Intel processors based on the Nehalem microarchitecture?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

#define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20

Package. Uncore B-box 0 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22

Package. Uncore B-box 0 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21

Package. Uncore B-box 0 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31

Package. Uncore B-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);

Note: MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM.

#define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33

Package. Uncore B-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);

Note: MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM.

#define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35

Package. Uncore B-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);

Note: MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM.

#define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37

Package. Uncore B-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);

Note: MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM.

#define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30

Package. Uncore B-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32

Package. Uncore B-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34

Package. Uncore B-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36

Package. Uncore B-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_B0_PMON_MASK 0x00000E46

Package. Uncore B-box 0 perfmon local box mask MSR.

Parameters

ECX	MSR_NEHALEM_B0_PMON_MASK (0x00000E46)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);
AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);

Note: MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM.

#define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45

Package. Uncore B-box 0 perfmon local box match MSR.

Parameters

ECX	MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);
AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);

Note: MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM.

#define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60

Package. Uncore B-box 1 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62

Package. Uncore B-box 1 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61

Package. Uncore B-box 1 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71

Package. Uncore B-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);

Note: MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM.

#define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73

Package. Uncore B-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);

Note: MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM.

#define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75

Package. Uncore B-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);

Note: MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM.

#define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77

Package. Uncore B-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);

Note: MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM.

#define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70

Package. Uncore B-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72

Package. Uncore B-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74

Package. Uncore B-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76

Package. Uncore B-box 1vperfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E

Package. Uncore B-box 1 perfmon local box mask MSR.

Parameters

ECX	MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);
AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);

Note: MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM.

#define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D

Package. Uncore B-box 1 perfmon local box match MSR.

Parameters

ECX	MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);
AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);

Note: MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM.

#define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00

Package. Uncore C-box 0 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02

Package. Uncore C-box 0 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01

Package. Uncore C-box 0 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11

Package. Uncore C-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);

Note: MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.

#define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13

Package. Uncore C-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);

Note: MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.

#define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15

Package. Uncore C-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);

Note: MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.

#define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17

Package. Uncore C-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);

Note: MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.

#define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19

Package. Uncore C-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);

Note: MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM.

#define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B

Package. Uncore C-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);

Note: MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM.

#define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10

Package. Uncore C-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12

Package. Uncore C-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14

Package. Uncore C-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16

Package. Uncore C-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18

Package. Uncore C-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);

Note: MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM.

#define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A

Package. Uncore C-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);
AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);

Note: MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM.

#define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80

Package. Uncore C-box 1 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82

Package. Uncore C-box 1 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81

Package. Uncore C-box 1 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91

Package. Uncore C-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);

Note: MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.

#define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93

Package. Uncore C-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);

Note: MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.

#define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95

Package. Uncore C-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);

Note: MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.

#define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97

Package. Uncore C-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);

Note: MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.

#define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99

Package. Uncore C-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);

Note: MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM.

#define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B

Package. Uncore C-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);

Note: MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM.

#define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90

Package. Uncore C-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92

Package. Uncore C-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94

Package. Uncore C-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96

Package. Uncore C-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98

Package. Uncore C-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);

Note: MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM.

#define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A

Package. Uncore C-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);
AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);

Note: MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM.

#define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40

Package. Uncore C-box 2 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42

Package. Uncore C-box 2 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41

Package. Uncore C-box 2 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51

Package. Uncore C-box 2 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);

Note: MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.

#define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53

Package. Uncore C-box 2 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);

Note: MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.

#define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55

Package. Uncore C-box 2 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);

Note: MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.

#define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57

Package. Uncore C-box 2 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);

Note: MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.

#define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59

Package. Uncore C-box 2 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);

Note: MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM.

#define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B

Package. Uncore C-box 2 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);

Note: MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM.

#define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50

Package. Uncore C-box 2 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52

Package. Uncore C-box 2 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54

Package. Uncore C-box 2 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56

Package. Uncore C-box 2 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58

Package. Uncore C-box 2 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);

Note: MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM.

#define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A

Package. Uncore C-box 2 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);
AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);

Note: MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM.

#define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0

Package. Uncore C-box 3 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2

Package. Uncore C-box 3 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1

Package. Uncore C-box 3 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1

Package. Uncore C-box 3 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);

Note: MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.

#define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3

Package. Uncore C-box 3 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);

Note: MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.

#define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5

Package. Uncore C-box 3 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);

Note: MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.

#define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7

Package. Uncore C-box 3 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);

Note: MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.

#define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9

Package. Uncore C-box 3 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);

Note: MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM.

#define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB

Package. Uncore C-box 3 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);

Note: MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM.

#define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0

Package. Uncore C-box 3 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2

Package. Uncore C-box 3 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4

Package. Uncore C-box 3 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6

Package. Uncore C-box 3 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8

Package. Uncore C-box 3 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);

Note: MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM.

#define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA

Package. Uncore C-box 3 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);
AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);

Note: MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM.

#define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20

Package. Uncore C-box 4 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22

Package. Uncore C-box 4 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21

Package. Uncore C-box 4 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31

Package. Uncore C-box 4 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);

Note: MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.

#define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33

Package. Uncore C-box 4 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);

Note: MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.

#define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35

Package. Uncore C-box 4 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);

Note: MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.

#define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37

Package. Uncore C-box 4 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);

Note: MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.

#define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39

Package. Uncore C-box 4 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);

Note: MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM.

#define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B

Package. Uncore C-box 4 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);

Note: MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM.

#define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30

Package. Uncore C-box 4 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32

Package. Uncore C-box 4 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34

Package. Uncore C-box 4 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36

Package. Uncore C-box 4 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38

Package. Uncore C-box 4 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);

Note: MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM.

#define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A

Package. Uncore C-box 4 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);
AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);

Note: MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM.

#define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0

Package. Uncore C-box 5 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2

Package. Uncore C-box 5 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1

Package. Uncore C-box 5 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1

Package. Uncore C-box 5 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);

Note: MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.

#define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3

Package. Uncore C-box 5 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);

Note: MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.

#define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5

Package. Uncore C-box 5 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);

Note: MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.

#define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7

Package. Uncore C-box 5 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);

Note: MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.

#define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9

Package. Uncore C-box 5 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);

Note: MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM.

#define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB

Package. Uncore C-box 5 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);

Note: MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM.

#define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0

Package. Uncore C-box 5 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2

Package. Uncore C-box 5 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4

Package. Uncore C-box 5 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6

Package. Uncore C-box 5 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8

Package. Uncore C-box 5 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);

Note: MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM.

#define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA

Package. Uncore C-box 5 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);
AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);

Note: MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM.

#define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60

Package. Uncore C-box 6 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62

Package. Uncore C-box 6 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61

Package. Uncore C-box 6 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71

Package. Uncore C-box 6 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);

Note: MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.

#define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73

Package. Uncore C-box 6 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);

Note: MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.

#define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75

Package. Uncore C-box 6 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);

Note: MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.

#define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77

Package. Uncore C-box 6 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);

Note: MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.

#define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79

Package. Uncore C-box 6 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);

Note: MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM.

#define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B

Package. Uncore C-box 6 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);

Note: MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM.

#define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70

Package. Uncore C-box 6 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72

Package. Uncore C-box 6 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74

Package. Uncore C-box 6 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76

Package. Uncore C-box 6 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78

Package. Uncore C-box 6 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);

Note: MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM.

#define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A

Package. Uncore C-box 6 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);
AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);

Note: MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM.

#define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0

Package. Uncore C-box 7 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2

Package. Uncore C-box 7 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1

Package. Uncore C-box 7 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1

Package. Uncore C-box 7 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);

Note: MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.

#define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3

Package. Uncore C-box 7 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);

Note: MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.

#define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5

Package. Uncore C-box 7 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);

Note: MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.

#define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7

Package. Uncore C-box 7 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);

Note: MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.

#define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9

Package. Uncore C-box 7 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);

Note: MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM.

#define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB

Package. Uncore C-box 7 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);

Note: MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM.

#define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0

Package. Uncore C-box 7 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2

Package. Uncore C-box 7 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4

Package. Uncore C-box 7 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6

Package. Uncore C-box 7 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8

Package. Uncore C-box 7 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);

Note: MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM.

#define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA

Package. Uncore C-box 7 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);
AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);

Note: MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM.

#define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC

Core. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3 Residency Counter. (R/O) Value since last reset that this core is in processor-specific C3 states. Count at the same frequency as the TSC.

Parameters

ECX	MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);
AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);

Note: MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.

#define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD

Core. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6 Residency Counter. (R/O) Value since last reset that this core is in processor-specific C6 states. Count at the same frequency as the TSC.

Parameters

ECX	MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);
AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);

Note: MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.

#define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301

Package.

Parameters

ECX	MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.

Example usage

MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);
AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);

Note: MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM.

#define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0

Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.

Parameters

ECX	MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.

Example usage

MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);

Note: MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.

#define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689

Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 17.4.8.1.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_FROM_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9

Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction.

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_n_TO_IP
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);

Note: MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.

#define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9

Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP (at 680H).

Parameters

ECX	MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);

Note: MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.

#define MSR_NEHALEM_LBR_SELECT 0x000001C8

Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2, "Filtering of Last Branch Records.".

Parameters

ECX	MSR_NEHALEM_LBR_SELECT (0x000001C8)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.

Example usage

MSR_NEHALEM_LBR_SELECT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);
AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);

Note: MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.

#define MSR_NEHALEM_LER_FROM_LIP 0x000001DD

Thread. Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.

Parameters

ECX	MSR_NEHALEM_LER_FROM_LIP (0x000001DD)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);

Note: MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.

#define MSR_NEHALEM_LER_TO_LIP 0x000001DE

Thread. Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.

Parameters

ECX	MSR_NEHALEM_LER_TO_LIP (0x000001DE)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);

Note: MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.

#define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56

Package. Uncore M-box 0 perfmon local box address mask MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);

Note: MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM.

#define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55

Package. Uncore M-box 0 perfmon local box address match MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);

Note: MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM.

#define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0

Package. Uncore M-box 0 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2

Package. Uncore M-box 0 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1

Package. Uncore M-box 0 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1

Package. Uncore M-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);

Note: MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM.

#define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3

Package. Uncore M-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);

Note: MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM.

#define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5

Package. Uncore M-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);

Note: MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM.

#define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7

Package. Uncore M-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);

Note: MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM.

#define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9

Package. Uncore M-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);

Note: MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM.

#define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB

Package. Uncore M-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);

Note: MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM.

#define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5

Package. Uncore M-box 0 perfmon DSP unit select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);

Note: MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM.

#define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0

Package. Uncore M-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2

Package. Uncore M-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4

Package. Uncore M-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6

Package. Uncore M-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8

Package. Uncore M-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);

Note: MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM.

#define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA

Package. Uncore M-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);

Note: MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM.

#define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6

Package. Uncore M-box 0 perfmon ISS unit select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);

Note: MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM.

#define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7

Package. Uncore M-box 0 perfmon MAP unit select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);

Note: MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM.

#define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54

Package. Uncore M-box 0 perfmon local box address match/mask config MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);

Note: MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM.

#define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8

Package. Uncore M-box 0 perfmon MIC THR select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);

Note: MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM.

#define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9

Package. Uncore M-box 0 perfmon PGT unit select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);

Note: MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM.

#define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA

Package. Uncore M-box 0 perfmon PLD unit select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);

Note: MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM.

#define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4

Package. Uncore M-box 0 perfmon time stamp unit select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);

Note: MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM.

#define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB

Package. Uncore M-box 0 perfmon ZDP unit select MSR.

Parameters

ECX	MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);
AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);

Note: MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM.

#define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E

Package. Uncore M-box 1 perfmon local box address mask MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);

Note: MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM.

#define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D

Package. Uncore M-box 1 perfmon local box address match MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);

Note: MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM.

#define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0

Package. Uncore M-box 1 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2

Package. Uncore M-box 1 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1

Package. Uncore M-box 1 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1

Package. Uncore M-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);

Note: MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM.

#define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3

Package. Uncore M-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);

Note: MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM.

#define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5

Package. Uncore M-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);

Note: MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM.

#define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7

Package. Uncore M-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);

Note: MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM.

#define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9

Package. Uncore M-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);

Note: MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM.

#define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB

Package. Uncore M-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);

Note: MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM.

#define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5

Package. Uncore M-box 1 perfmon DSP unit select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);

Note: MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM.

#define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0

Package. Uncore M-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2

Package. Uncore M-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4

Package. Uncore M-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6

Package. Uncore M-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8

Package. Uncore M-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);

Note: MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM.

#define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA

Package. Uncore M-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);

Note: MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM.

#define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6

Package. Uncore M-box 1 perfmon ISS unit select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);

Note: MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM.

#define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7

Package. Uncore M-box 1 perfmon MAP unit select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);

Note: MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM.

#define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C

Package. Uncore M-box 1 perfmon local box address match/mask config MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);

Note: MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM.

#define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8

Package. Uncore M-box 1 perfmon MIC THR select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);

Note: MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM.

#define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9

Package. Uncore M-box 1 perfmon PGT unit select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);

Note: MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM.

#define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA

Package. Uncore M-box 1 perfmon PLD unit select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);

Note: MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM.

#define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4

Package. Uncore M-box 1 perfmon time stamp unit select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);

Note: MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM.

#define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB

Package. Uncore M-box 1 perfmon ZDP unit select MSR.

Parameters

ECX	MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);
AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);

Note: MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM.

#define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4

Miscellaneous Feature Control (R/W).

Parameters

ECX	MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.

Example usage

MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);
AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);

Note: MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.

#define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA

See http://biosbits.org.

Parameters

ECX	MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.

Example usage

MSR_NEHALEM_MISC_PWR_MGMT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);
AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);

Note: MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.

#define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6

Thread. Offcore Response Event Select Register (R/W).

Parameters

ECX	MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);
AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);

Note: MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.

#define MSR_NEHALEM_PEBS_ENABLE 0x000003F1

Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".

Parameters

ECX	MSR_NEHALEM_PEBS_ENABLE (0x000003F1)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.

Example usage

MSR_NEHALEM_PEBS_ENABLE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);
AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);

Note: MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.

#define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6

Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring Facility.".

Parameters

ECX	MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.

Example usage

MSR_NEHALEM_PEBS_LD_LAT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);
AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);

Note: MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.

#define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390

Thread. (R/W).

Parameters

ECX	MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.

Example usage

MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);

Note: MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.

#define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E

Thread. (RO).

Parameters

ECX	MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.

Example usage

MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);

Note: MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.

#define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C3 states. Count at the same frequency as the TSC.

Parameters

ECX	MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);
AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);

Note: MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.

#define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C6 states. Count at the same frequency as the TSC.

Parameters

ECX	MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);
AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);

Note: MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.

#define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C7 states. Count at the same frequency as the TSC.

Parameters

ECX	MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);
AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);

Note: MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.

#define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2

Core. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. See http://biosbits.org.

Parameters

ECX	MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.

Example usage

MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);

Note: MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.

#define MSR_NEHALEM_PLATFORM_ID 0x00000017

Package. Model Specific Platform ID (R).

Parameters

ECX	MSR_NEHALEM_PLATFORM_ID (0x00000017)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.

Example usage

MSR_NEHALEM_PLATFORM_ID_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);

Note: MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.

#define MSR_NEHALEM_PLATFORM_INFO 0x000000CE

Package. see http://biosbits.org.

Parameters

ECX	MSR_NEHALEM_PLATFORM_INFO (0x000000CE)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.

Example usage

MSR_NEHALEM_PLATFORM_INFO_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);
AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);

Note: MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.

#define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4

Core. Power Management IO Redirection in C-state (R/W) See http://biosbits.org.

Parameters

ECX	MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.

Example usage

MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);
AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);

Note: MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.

#define MSR_NEHALEM_POWER_CTL 0x000001FC

Core. Power Control Register. See http://biosbits.org.

Parameters

ECX	MSR_NEHALEM_POWER_CTL (0x000001FC)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.

Example usage

MSR_NEHALEM_POWER_CTL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);
AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);

Note: MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.

#define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00

Package. Uncore R-box 0 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02

Package. Uncore R-box 0 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01

Package. Uncore R-box 0 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11

Package. Uncore R-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);

Note: MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM.

#define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13

Package. Uncore R-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);

Note: MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM.

#define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15

Package. Uncore R-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);

Note: MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM.

#define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17

Package. Uncore R-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);

Note: MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM.

#define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19

Package. Uncore R-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);

Note: MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM.

#define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B

Package. Uncore R-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);

Note: MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM.

#define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D

Package. Uncore R-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);

Note: MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM.

#define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F

Package. Uncore R-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);

Note: MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM.

#define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10

Package. Uncore R-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12

Package. Uncore R-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14

Package. Uncore R-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16

Package. Uncore R-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18

Package. Uncore R-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);

Note: MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM.

#define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A

Package. Uncore R-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);

Note: MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM.

#define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C

Package. Uncore R-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);

Note: MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM.

#define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E

Package. Uncore R-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);

Note: MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM.

#define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04

Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);

Note: MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM.

#define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05

Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);

Note: MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM.

#define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06

Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);

Note: MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM.

#define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07

Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);

Note: MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM.

#define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08

Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);

Note: MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM.

#define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09

Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);

Note: MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM.

#define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A

Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);

Note: MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM.

#define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B

Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);

Note: MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM.

#define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C

Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);

Note: MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM.

#define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D

Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);

Note: MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM.

#define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E

Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);

Note: MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM.

#define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F

Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.

Parameters

ECX	MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);
AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);

Note: MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM.

#define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20

Package. Uncore R-box 1 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22

Package. Uncore R-box 1 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21

Package. Uncore R-box 1 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35

Package. Uncore R-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);

Note: MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM.

#define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37

Package. Uncore R-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);

Note: MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM.

#define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39

Package. Uncore R-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);

Note: MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM.

#define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B

Package. Uncore R-box 1perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);

Note: MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM.

#define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D

Package. Uncore R-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);

Note: MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM.

#define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F

Package. Uncore R-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);

Note: MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM.

#define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31

Package. Uncore R-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);

Note: MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM.

#define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33

Package. Uncore R-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);

Note: MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM.

#define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34

Package. Uncore R-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);

Note: MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM.

#define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36

Package. Uncore R-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);

Note: MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM.

#define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38

Package. Uncore R-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);

Note: MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM.

#define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A

Package. Uncore R-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);

Note: MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM.

#define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C

Package. Uncore R-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);

Note: MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM.

#define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E

Package. Uncore R-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);

Note: MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM.

#define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30

Package. Uncore R-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);

Note: MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM.

#define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32

Package. Uncore R-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);

Note: MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM.

#define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26

Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);

Note: MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM.

#define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27

Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);

Note: MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM.

#define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28

Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);

Note: MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM.

#define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29

Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);

Note: MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM.

#define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A

Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);

Note: MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM.

#define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B

Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);

Note: MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM.

#define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24

Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);

Note: MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM.

#define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25

Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);

Note: MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM.

#define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C

Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);

Note: MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM.

#define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D

Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);

Note: MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM.

#define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E

Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);

Note: MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM.

#define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F

Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.

Parameters

ECX	MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);
AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);

Note: MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM.

#define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40

Package. Uncore S-box 0 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42

Package. Uncore S-box 0 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41

Package. Uncore S-box 0 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51

Package. Uncore S-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);

Note: MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.

#define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53

Package. Uncore S-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);

Note: MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.

#define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55

Package. Uncore S-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);

Note: MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.

#define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57

Package. Uncore S-box 0 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);

Note: MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.

#define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50

Package. Uncore S-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52

Package. Uncore S-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54

Package. Uncore S-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56

Package. Uncore S-box 0 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A

Package. Uncore S-box 0 perfmon local box mask MSR.

Parameters

ECX	MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);
AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);

Note: MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM.

#define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49

Package. Uncore S-box 0 perfmon local box match MSR.

Parameters

ECX	MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);
AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);

Note: MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM.

#define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0

Package. Uncore S-box 1 perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2

Package. Uncore S-box 1 perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1

Package. Uncore S-box 1 perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1

Package. Uncore S-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);

Note: MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.

#define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3

Package. Uncore S-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);

Note: MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.

#define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5

Package. Uncore S-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);

Note: MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.

#define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7

Package. Uncore S-box 1 perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);

Note: MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.

#define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0

Package. Uncore S-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2

Package. Uncore S-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4

Package. Uncore S-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6

Package. Uncore S-box 1 perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A

Package. Uncore S-box 1 perfmon local box mask MSR.

Parameters

ECX	MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);
AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);

Note: MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM.

#define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59

Package. Uncore S-box 1 perfmon local box match MSR.

Parameters

ECX	MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);
AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);

Note: MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM.

#define MSR_NEHALEM_SMI_COUNT 0x00000034

Thread. SMI Counter (R/O).

Parameters

ECX	MSR_NEHALEM_SMI_COUNT (0x00000034)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.

Example usage

MSR_NEHALEM_SMI_COUNT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);

Note: MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.

#define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2

Thread.

Parameters

ECX	MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.

Example usage

MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);
AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);

Note: MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.

#define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC

See http://biosbits.org.

Parameters

ECX	MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.

Example usage

MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);
AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);

Note: MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.

#define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters

ECX	MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)
EAX	Lower 32-bits of MSR value. Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.

Example usage

MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);

Note: MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.

#define MSR_NEHALEM_U_PMON_CTR 0x00000C11

Package. Uncore U-box perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_U_PMON_CTR (0x00000C11)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);
AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);

Note: MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM.

#define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10

Package. Uncore U-box perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);
AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);

Note: MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM.

#define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00

Package. Uncore U-box perfmon global control MSR.

Parameters

ECX	MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);

Note: MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM.

#define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02

Package. Uncore U-box perfmon global overflow control MSR.

Parameters

ECX	MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);

Note: MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM.

#define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01

Package. Uncore U-box perfmon global status MSR.

Parameters

ECX	MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);

Note: MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM.

#define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396

Package. See Section 18.3.1.2.3, "Uncore Address/Opcode Match MSR.".

Parameters

ECX	MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);

Note: MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM.

#define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394

Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);

Note: MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM.

#define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395

Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);

Note: MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM.

#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391

Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);

Note: MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM.

#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393

Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);

Note: MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM.

#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392

Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);

Note: MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM.

#define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PERFEVTSELi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);

Note: MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.

#define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PERFEVTSELi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);

Note: MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.

#define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PERFEVTSELi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);

Note: MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.

#define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PERFEVTSELi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);

Note: MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.

#define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PERFEVTSELi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);

Note: MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.

#define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PERFEVTSELi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);

Note: MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.

#define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PERFEVTSELi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);

Note: MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.

#define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PERFEVTSELi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);

Note: MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM. MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.

#define MSR_NEHALEM_UNCORE_PMC0 0x000003B0

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PMCi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);

Note: MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM. MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM. MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM. MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM. MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM. MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM. MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM. MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.

#define MSR_NEHALEM_UNCORE_PMC1 0x000003B1

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PMCi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);

Note: MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM. MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM. MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM. MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM. MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM. MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM. MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM. MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.

#define MSR_NEHALEM_UNCORE_PMC2 0x000003B2

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PMCi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);

Note: MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM. MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM. MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM. MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM. MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM. MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM. MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM. MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.

#define MSR_NEHALEM_UNCORE_PMC3 0x000003B3

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PMCi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);

Note: MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM. MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM. MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM. MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM. MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM. MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM. MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM. MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.

#define MSR_NEHALEM_UNCORE_PMC4 0x000003B4

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PMCi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);

Note: MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM. MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM. MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM. MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM. MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM. MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM. MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM. MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.

#define MSR_NEHALEM_UNCORE_PMC5 0x000003B5

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PMCi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);

Note: MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM. MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM. MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM. MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM. MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM. MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM. MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM. MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.

#define MSR_NEHALEM_UNCORE_PMC6 0x000003B6

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PMCi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);

Note: MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM. MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM. MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM. MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM. MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM. MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM. MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM. MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.

#define MSR_NEHALEM_UNCORE_PMC7 0x000003B7

Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration Facility.".

Parameters

ECX	MSR_NEHALEM_UNCORE_PMCi
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);

Note: MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM. MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM. MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM. MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM. MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM. MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM. MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM. MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.

#define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80

Package. Uncore W-box perfmon local box control MSR.

Parameters

ECX	MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);

Note: MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM.

#define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82

Package. Uncore W-box perfmon local box overflow control MSR.

Parameters

ECX	MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);

Note: MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM.

#define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81

Package. Uncore W-box perfmon local box status MSR.

Parameters

ECX	MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);

Note: MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM.

#define MSR_NEHALEM_W_PMON_CTR0 0x00000C91

Package. Uncore W-box perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);
AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);

Note: MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM.

#define MSR_NEHALEM_W_PMON_CTR1 0x00000C93

Package. Uncore W-box perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);
AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);

Note: MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM.

#define MSR_NEHALEM_W_PMON_CTR2 0x00000C95

Package. Uncore W-box perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);
AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);

Note: MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM.

#define MSR_NEHALEM_W_PMON_CTR3 0x00000C97

Package. Uncore W-box perfmon counter MSR.

Parameters

ECX	MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);
AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);

Note: MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM.

#define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90

Package. Uncore W-box perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);

Note: MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM.

#define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92

Package. Uncore W-box perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);
AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);

Note: MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM.

#define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94

Package. Uncore W-box perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);
AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);

Note: MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM.

#define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96

Package. Uncore W-box perfmon event select MSR.

Parameters

ECX	MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);
AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);

Note: MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM.

#define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394

Package. Uncore W-box perfmon fixed counter.

Parameters

ECX	MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);
AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);

Note: MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM.

#define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395

Package. Uncore U-box perfmon fixed counter control MSR.

Parameters

ECX	MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);
AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);

Note: MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM.

Data Structures

Macros

Detailed Description

Macro Definition Documentation