MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Union Reference

Data Fields
struct {
UINT32   FastStrings:1
UINT32   Reserved1:2
UINT32   AutomaticThermalControlCircuit:1
UINT32   Reserved2:3
UINT32   PerformanceMonitoring:1
UINT32   Reserved3:3
UINT32   BTS:1
UINT32   PEBS:1
UINT32   Reserved4:3
UINT32   EIST:1
UINT32   Reserved5:1
UINT32   MONITOR:1
UINT32   Reserved6:3
UINT32   LimitCpuidMaxval:1
UINT32   xTPR_Message_Disable:1
UINT32   Reserved7:8
UINT32   Reserved8:2
UINT32   XD:1
UINT32   Reserved9:3
UINT32   TurboModeDisable:1
UINT32   Reserved10:25
}	Bits
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_NEHALEM_IA32_MISC_ENABLE

Field Documentation

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See Table 2-2. Default value is 1.

struct { ... } MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Thread. Fast-Strings Enable See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Reserved1

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Reserved10

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Reserved2

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Reserved3

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Reserved4

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Reserved5

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Reserved6

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Reserved7

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Reserved8

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Reserved9

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::TurboModeDisable

[Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors that support Intel Turbo Boost Technology, the turbo mode feature is disabled and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor's support of turbo mode is enabled. Note: the power-on default value is used by BIOS to detect hardware support of turbo mode. If power-on default value is 1, turbo mode is available in the processor. If power-on default value is 0, turbo mode is not available.

UINT64 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.