MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Union Reference

Data Fields
struct {
UINT32   EISTHardwareCoordinationDisable:1
UINT32   EnergyPerformanceBiasEnable:1
UINT32   Reserved1:30
UINT32   Reserved2:32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_NEHALEM_MISC_PWR_MGMT

Field Documentation

struct { ... } MSR_NEHALEM_MISC_PWR_MGMT_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER::EISTHardwareCoordinationDisable

[Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0, enables hardware coordination of Enhanced Intel Speedstep Technology request from processor cores; When 1, disables hardware coordination of Enhanced Intel Speedstep Technology requests.

UINT32 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER::EnergyPerformanceBiasEnable

[Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with Ring 0 privileges. This bit's status (1 or 0) is also reflected by CPUID.(EAX=06h):ECX[3].

UINT32 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER::Reserved1

UINT32 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER::Reserved2

UINT32 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER::Uint64

All bit fields as a 64-bit value