Data Structures
union	MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER

union	MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER

union	MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER

union	MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER

union	MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER

union	MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER

union	MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER

union	MSR_IVY_BRIDGE_PPIN_CTL_REGISTER

union	MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER

union	MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER

union	MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER

union	MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER

union	MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER

union	MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER

Macros
#define	IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel)

#define	MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE

#define	MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2

#define	MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639

#define	MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648

#define	MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649

#define	MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A

#define	MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B

#define	MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C

#define	MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E

#define	MSR_IVY_BRIDGE_PPIN 0x0000004F

#define	MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE

#define	MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F

#define	MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2

#define	MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE

#define	MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B

#define	MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613

#define	MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618

#define	MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619

#define	MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B

#define	MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C

#define	MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1

#define	MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00

#define	MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01

#define	MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06

#define	MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15

#define	MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35

#define	MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A

#define	MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A

#define	MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A

#define	MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A

#define	MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A

#define	MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA

#define	MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA

#define	MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA

#define	MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04

#define	MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10

#define	MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11

#define	MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12

#define	MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13

#define	MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14

#define	MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16

#define	MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17

#define	MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18

#define	MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19

#define	MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A

#define	MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24

#define	MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30

#define	MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31

#define	MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32

#define	MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33

#define	MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34

#define	MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36

#define	MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37

#define	MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38

#define	MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39

#define	MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A

#define	MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44

#define	MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50

#define	MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51

#define	MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52

#define	MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53

#define	MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54

#define	MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56

#define	MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57

#define	MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58

#define	MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59

#define	MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A

#define	MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64

#define	MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70

#define	MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71

#define	MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72

#define	MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73

#define	MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74

#define	MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76

#define	MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77

#define	MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78

#define	MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79

#define	MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A

#define	MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84

#define	MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90

#define	MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91

#define	MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92

#define	MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93

#define	MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94

#define	MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96

#define	MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97

#define	MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98

#define	MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99

#define	MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A

#define	MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4

#define	MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0

#define	MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1

#define	MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2

#define	MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3

#define	MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4

#define	MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6

#define	MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7

#define	MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8

#define	MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9

#define	MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA

#define	MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4

#define	MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0

#define	MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1

#define	MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2

#define	MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3

#define	MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4

#define	MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6

#define	MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7

#define	MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8

#define	MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9

#define	MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA


#define	MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474

#define	MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478

#define	MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C


#define	MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475

#define	MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479

#define	MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D


#define	MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476

#define	MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A

#define	MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E


#define	MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477

#define	MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B

#define	MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F

Detailed Description

MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_IVY_BRIDGE_PROCESSOR	(	DisplayFamily,
		DisplayModel
	)

Value:

(DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x3A || \
    DisplayModel == 0x3E    \
    )                       \
   )

Is Intel processors based on the Ivy Bridge microarchitecture?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A

Package. Uncore C-box 0 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44

Package. Uncore C-box 10 perfmon local box wide control.

Parameters

ECX	MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);

Note: MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.

#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54

Package. Uncore C-box 10 perfmon box wide filter.

Parameters

ECX	MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);

Note: MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.

#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A

Package. Uncore C-box 10 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56

Package. Uncore C-box 10 perfmon counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);

Note: MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.

#define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57

Package. Uncore C-box 10 perfmon counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);

Note: MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.

#define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58

Package. Uncore C-box 10 perfmon counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);

Note: MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.

#define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59

Package. Uncore C-box 10 perfmon counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);

Note: MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.

#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50

Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);

Note: MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.

#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51

Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);

Note: MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.

#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52

Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);

Note: MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.

#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53

Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);

Note: MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.

#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64

Package. Uncore C-box 11 perfmon local box wide control.

Parameters

ECX	MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);

Note: MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.

#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74

Package. Uncore C-box 11 perfmon box wide filter.

Parameters

ECX	MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);

Note: MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.

#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A

Package. Uncore C-box 11 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76

Package. Uncore C-box 11 perfmon counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);

Note: MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.

#define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77

Package. Uncore C-box 11 perfmon counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);

Note: MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.

#define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78

Package. Uncore C-box 11 perfmon counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);

Note: MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.

#define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79

Package. Uncore C-box 11 perfmon counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);

Note: MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.

#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70

Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);

Note: MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.

#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71

Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);

Note: MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.

#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72

Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);

Note: MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.

#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73

Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);

Note: MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.

#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84

Package. Uncore C-box 12 perfmon local box wide control.

Parameters

ECX	MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);

Note: MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.

#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94

Package. Uncore C-box 12 perfmon box wide filter.

Parameters

ECX	MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);

Note: MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.

#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A

Package. Uncore C-box 12 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96

Package. Uncore C-box 12 perfmon counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);

Note: MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.

#define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97

Package. Uncore C-box 12 perfmon counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);

Note: MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.

#define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98

Package. Uncore C-box 12 perfmon counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);

Note: MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.

#define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99

Package. Uncore C-box 12 perfmon counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);

Note: MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.

#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90

Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);

Note: MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.

#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91

Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);

Note: MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.

#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92

Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);

Note: MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.

#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93

Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);

Note: MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.

#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4

Package. Uncore C-box 13 perfmon local box wide control.

Parameters

ECX	MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);

Note: MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.

#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4

Package. Uncore C-box 13 perfmon box wide filter.

Parameters

ECX	MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);

Note: MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.

#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA

Package. Uncore C-box 13 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6

Package. Uncore C-box 13 perfmon counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);

Note: MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.

#define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7

Package. Uncore C-box 13 perfmon counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);

Note: MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.

#define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8

Package. Uncore C-box 13 perfmon counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);

Note: MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.

#define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9

Package. Uncore C-box 13 perfmon counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);

Note: MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.

#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0

Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);

Note: MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.

#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1

Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);

Note: MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.

#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2

Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);

Note: MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.

#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3

Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);

Note: MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.

#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4

Package. Uncore C-box 14 perfmon local box wide control.

Parameters

ECX	MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);

Note: MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.

#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4

Package. Uncore C-box 14 perfmon box wide filter.

Parameters

ECX	MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);

Note: MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.

#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA

Package. Uncore C-box 14 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6

Package. Uncore C-box 14 perfmon counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);

Note: MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.

#define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7

Package. Uncore C-box 14 perfmon counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);

Note: MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.

#define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8

Package. Uncore C-box 14 perfmon counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);

Note: MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.

#define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9

Package. Uncore C-box 14 perfmon counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);

Note: MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.

#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0

Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);

Note: MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.

#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1

Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);

Note: MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.

#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2

Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);

Note: MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.

#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3

Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);

Note: MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.

#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A

Package. Uncore C-box 1 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A

Package. Uncore C-box 2 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A

Package. Uncore C-box 3 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A

Package. Uncore C-box 4 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA

Package. Uncore C-box 5 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA

Package. Uncore C-box 6 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA

Package. Uncore C-box 7 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04

Package. Uncore C-box 8 perfmon local box wide control.

Parameters

ECX	MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);

Note: MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.

#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14

Package. Uncore C-box 8 perfmon box wide filter.

Parameters

ECX	MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);

Note: MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.

#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A

Package. Uncore C-box 8 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16

Package. Uncore C-box 8 perfmon counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);

Note: MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.

#define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17

Package. Uncore C-box 8 perfmon counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);

Note: MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.

#define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18

Package. Uncore C-box 8 perfmon counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);

Note: MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.

#define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19

Package. Uncore C-box 8 perfmon counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);

Note: MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.

#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10

Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);

Note: MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.

#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11

Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);

Note: MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.

#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12

Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);

Note: MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.

#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13

Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);

Note: MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.

#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24

Package. Uncore C-box 9 perfmon local box wide control.

Parameters

ECX	MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);

Note: MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.

#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34

Package. Uncore C-box 9 perfmon box wide filter.

Parameters

ECX	MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);

Note: MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.

#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A

Package. Uncore C-box 9 perfmon box wide filter1.

Parameters

ECX	MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);

Note: MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.

#define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36

Package. Uncore C-box 9 perfmon counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);

Note: MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.

#define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37

Package. Uncore C-box 9 perfmon counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);

Note: MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.

#define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38

Package. Uncore C-box 9 perfmon counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);

Note: MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.

#define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39

Package. Uncore C-box 9 perfmon counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);

Note: MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.

#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30

Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.

Parameters

ECX	MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);

Note: MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.

#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31

Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.

Parameters

ECX	MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);

Note: MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.

#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32

Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.

Parameters

ECX	MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);

Note: MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.

#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33

Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.

Parameters

ECX	MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);

Note: MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.

#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B

Package. ConfigTDP Control (R/W).

Parameters

ECX	MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.

Example usage

MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);

Note: MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.

#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649

Package. ConfigTDP Level 1 ratio and power level (R/O).

Parameters

ECX	MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.

Example usage

MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);

Note: MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.

#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A

Package. ConfigTDP Level 2 ratio and power level (R/O).

Parameters

ECX	MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.

Example usage

MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);

Note: MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.

#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648

Package. Base TDP Ratio (R/O).

Parameters

ECX	MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.

Example usage

MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);

Note: MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.

#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619

Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);

Note: MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.

#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B

Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);

Note: MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.

#define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C

Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);
AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);

Note: MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.

#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618

Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);
AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);

Note: MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.

#define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F

Package. MC Bank Error Configuration (R/W).

Parameters

ECX	MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.

Example usage

MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);

Note: MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.

#define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476

Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 15.3.2.4, "IA32_MCi_MISC MSRs.".

Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) and its corresponding slice of L3.

Parameters

ECX	MSR_IVY_BRIDGE_IA32_MCi_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);
AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);

Note: MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM. MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM. MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.

#define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474

Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 15.3.2.4, "IA32_MCi_MISC MSRs.".

Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) and its corresponding slice of L3.

Parameters

ECX	MSR_IVY_BRIDGE_IA32_MCi_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);

Note: MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM. MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM. MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.

#define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477

Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 15.3.2.4, "IA32_MCi_MISC MSRs.".

Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) and its corresponding slice of L3.

Parameters

ECX	MSR_IVY_BRIDGE_IA32_MCi_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);
AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);

Note: MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM. MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM. MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.

#define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475

Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 15.3.2.4, "IA32_MCi_MISC MSRs.".

Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) and its corresponding slice of L3.

Parameters

ECX	MSR_IVY_BRIDGE_IA32_MCi_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);
AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);

Note: MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM. MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM. MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.

#define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A

Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 15.3.2.4, "IA32_MCi_MISC MSRs.".

Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) and its corresponding slice of L3.

Parameters

ECX	MSR_IVY_BRIDGE_IA32_MCi_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);
AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);

Note: MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM. MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM. MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.

#define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478

Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 15.3.2.4, "IA32_MCi_MISC MSRs.".

Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) and its corresponding slice of L3.

Parameters

ECX	MSR_IVY_BRIDGE_IA32_MCi_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);

Note: MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM. MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM. MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.

#define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B

Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 15.3.2.4, "IA32_MCi_MISC MSRs.".

Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) and its corresponding slice of L3.

Parameters

ECX	MSR_IVY_BRIDGE_IA32_MCi_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);
AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);

Note: MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM. MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM. MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.

#define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479

Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 15.3.2.4, "IA32_MCi_MISC MSRs.".

Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) and its corresponding slice of L3.

Parameters

ECX	MSR_IVY_BRIDGE_IA32_MCi_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);
AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);

Note: MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM. MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM. MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.

#define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E

Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 15.3.2.4, "IA32_MCi_MISC MSRs.".

Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) and its corresponding slice of L3.

Parameters

ECX	MSR_IVY_BRIDGE_IA32_MCi_ADDR
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);
AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);

Note: MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM. MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM. MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.

#define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C

Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 15.3.2.4, "IA32_MCi_MISC MSRs.".

Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) and its corresponding slice of L3.

Parameters

ECX	MSR_IVY_BRIDGE_IA32_MCi_CTL
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);

Note: MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM. MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM. MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.

#define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F

Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 15.3.2.4, "IA32_MCi_MISC MSRs.".

Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) and its corresponding slice of L3.

Parameters

ECX	MSR_IVY_BRIDGE_IA32_MCi_MISC
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);
AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);

Note: MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM. MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM. MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.

#define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D

Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 15.3.2.4, "IA32_MCi_MISC MSRs.".

Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) and its corresponding slice of L3.

Parameters

ECX	MSR_IVY_BRIDGE_IA32_MCi_STATUS
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);
AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);

Note: MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM. MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM. MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.

#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B

Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.

Parameters

ECX	MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.

Example usage

MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);

Note: MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.

#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35

Package. Uncore PCU perfmon box wide status.

Parameters

ECX	MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);

Note: MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.

#define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1

Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".

Parameters

ECX	MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.

Example usage

MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);
AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);

Note: MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.

#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2

Core. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. See http://biosbits.org.

Parameters

ECX	MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.

Example usage

MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);

Note: MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.

#define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613

Package. Package RAPL Perf Status (R/O).

Parameters

ECX	MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);

Note: MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.

#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE

Package. See http://biosbits.org.

Parameters

ECX	MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.

Example usage

MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);
AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);

Note: MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.

#define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE

Package. See http://biosbits.org.

Parameters

ECX	MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.

Example usage

MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);

Note: MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.

#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06

Package. Uncore perfmon per-socket global configuration.

Parameters

ECX	MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);
AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);

Note: MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.

#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00

Package. Uncore perfmon per-socket global control.

Parameters

ECX	MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);

Note: MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.

#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01

Package. Uncore perfmon per-socket global status.

Parameters

ECX	MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);
AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);

Note: MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.

#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639

Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters

ECX	MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS);

Note: MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.

#define MSR_IVY_BRIDGE_PPIN 0x0000004F

Package. Protected Processor Inventory Number (R/O). Protected Processor Inventory Number (R/O) A unique value within a given CPUID family/model/stepping signature that a privileged inventory initialization agent can access to identify each physical processor, when access to MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if MSR_PPIN_CTL[bits 1:0] = '10b'.

Parameters

ECX	MSR_IVY_BRIDGE_PPIN (0x0000004F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);

Note: MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.

#define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E

Package. Protected Processor Inventory Number Enable Control (R/W).

Parameters

ECX	MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.

Example usage

MSR_IVY_BRIDGE_PPIN_CTL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);

Note: MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.

#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2

Package.

Parameters

ECX	MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.

Example usage

MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);
AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);

Note: MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.

#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C

Package. ConfigTDP Control (R/W).

Parameters

ECX	MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.

Example usage

MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);
AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);

Note: MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.

#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters

ECX	MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)
EAX	Lower 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.

Example usage

MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);

Note: MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.

#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15

Package. Uncore U-box perfmon U-box wide status.

Parameters

ECX	MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);

Note: MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.

Data Structures

Macros

Detailed Description

Macro Definition Documentation