HaswellMsr.h File Reference

Data Structures
union	MSR_HASWELL_PLATFORM_INFO_REGISTER
union	MSR_HASWELL_IA32_PERFEVTSEL_REGISTER
union	MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER
union	MSR_HASWELL_LBR_SELECT_REGISTER
union	MSR_HASWELL_PKGC_IRTL1_REGISTER
union	MSR_HASWELL_PKGC_IRTL2_REGISTER
union	MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER
union	MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER
union	MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER
union	MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER
union	MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER
union	MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER
union	MSR_HASWELL_SMM_MCA_CAP_REGISTER
union	MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER
union	MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
union	MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER
union	MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER
union	MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER
union	MSR_HASWELL_UNC_CBO_CONFIG_REGISTER
union	MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER
union	MSR_HASWELL_RAPL_POWER_UNIT_REGISTER
union	MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
union	MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
union	MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
union	MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER
union	MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER
union	MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER

Macros
#define	IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel)
#define	MSR_HASWELL_PLATFORM_INFO   0x000000CE
#define	MSR_HASWELL_IA32_PERFEVTSEL2   0x00000188
#define	MSR_HASWELL_LBR_SELECT   0x000001C8
#define	MSR_HASWELL_PKGC_IRTL1   0x0000060B
#define	MSR_HASWELL_PKGC_IRTL2   0x0000060C
#define	MSR_HASWELL_PKG_PERF_STATUS   0x00000613
#define	MSR_HASWELL_DRAM_ENERGY_STATUS   0x00000619
#define	MSR_HASWELL_DRAM_PERF_STATUS   0x0000061B
#define	MSR_HASWELL_CONFIG_TDP_NOMINAL   0x00000648
#define	MSR_HASWELL_CONFIG_TDP_LEVEL1   0x00000649
#define	MSR_HASWELL_CONFIG_TDP_LEVEL2   0x0000064A
#define	MSR_HASWELL_CONFIG_TDP_CONTROL   0x0000064B
#define	MSR_HASWELL_TURBO_ACTIVATION_RATIO   0x0000064C
#define	MSR_HASWELL_PKG_CST_CONFIG_CONTROL   0x000000E2
#define	MSR_HASWELL_SMM_MCA_CAP   0x0000017D
#define	MSR_HASWELL_TURBO_RATIO_LIMIT   0x000001AD
#define	MSR_HASWELL_UNC_PERF_GLOBAL_CTRL   0x00000391
#define	MSR_HASWELL_UNC_PERF_GLOBAL_STATUS   0x00000392
#define	MSR_HASWELL_UNC_PERF_FIXED_CTRL   0x00000394
#define	MSR_HASWELL_UNC_PERF_FIXED_CTR   0x00000395
#define	MSR_HASWELL_UNC_CBO_CONFIG   0x00000396
#define	MSR_HASWELL_UNC_ARB_PERFCTR0   0x000003B0
#define	MSR_HASWELL_UNC_ARB_PERFCTR1   0x000003B1
#define	MSR_HASWELL_UNC_ARB_PERFEVTSEL0   0x000003B2
#define	MSR_HASWELL_UNC_ARB_PERFEVTSEL1   0x000003B3
#define	MSR_HASWELL_SMM_FEATURE_CONTROL   0x000004E0
#define	MSR_HASWELL_SMM_DELAYED   0x000004E2
#define	MSR_HASWELL_SMM_BLOCKED   0x000004E3
#define	MSR_HASWELL_RAPL_POWER_UNIT   0x00000606
#define	MSR_HASWELL_PP0_ENERGY_STATUS   0x00000639
#define	MSR_HASWELL_PP1_POWER_LIMIT   0x00000640
#define	MSR_HASWELL_PP1_ENERGY_STATUS   0x00000641
#define	MSR_HASWELL_PP1_POLICY   0x00000642
#define	MSR_HASWELL_CORE_PERF_LIMIT_REASONS   0x00000690
#define	MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS   0x000006B0
#define	MSR_HASWELL_RING_PERF_LIMIT_REASONS   0x000006B1
#define	MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0   0x00000700
#define	MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1   0x00000701
#define	MSR_HASWELL_UNC_CBO_0_PERFCTR0   0x00000706
#define	MSR_HASWELL_UNC_CBO_0_PERFCTR1   0x00000707
#define	MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0   0x00000710
#define	MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1   0x00000711
#define	MSR_HASWELL_UNC_CBO_1_PERFCTR0   0x00000716
#define	MSR_HASWELL_UNC_CBO_1_PERFCTR1   0x00000717
#define	MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0   0x00000720
#define	MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1   0x00000721
#define	MSR_HASWELL_UNC_CBO_2_PERFCTR0   0x00000726
#define	MSR_HASWELL_UNC_CBO_2_PERFCTR1   0x00000727
#define	MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0   0x00000730
#define	MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1   0x00000731
#define	MSR_HASWELL_UNC_CBO_3_PERFCTR0   0x00000736
#define	MSR_HASWELL_UNC_CBO_3_PERFCTR1   0x00000737
#define	MSR_HASWELL_PKG_C8_RESIDENCY   0x00000630
#define	MSR_HASWELL_PKG_C9_RESIDENCY   0x00000631
#define	MSR_HASWELL_PKG_C10_RESIDENCY   0x00000632
#define	MSR_HASWELL_IA32_PERFEVTSEL0   0x00000186
#define	MSR_HASWELL_IA32_PERFEVTSEL1   0x00000187
#define	MSR_HASWELL_IA32_PERFEVTSEL3   0x00000189

Detailed Description

MSR Definitions for Intel processors based on the Haswell microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:

Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_HASWELL_PROCESSOR	(		DisplayFamily,
			DisplayModel
	)

Value:

(DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x3C || \
    DisplayModel == 0x45 || \
    DisplayModel == 0x46    \
    )                       \
   )

Is Intel processors based on the Haswell microarchitecture?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

#define MSR_HASWELL_CONFIG_TDP_CONTROL   0x0000064B

Package. ConfigTDP Control (R/W).

Parameters

ECX	MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.

Example usage

MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);
AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);

Note

MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.

#define MSR_HASWELL_CONFIG_TDP_LEVEL1   0x00000649

Package. ConfigTDP Level 1 ratio and power level (R/O).

Parameters

ECX	MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.

Example usage

MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);

Note

MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.

#define MSR_HASWELL_CONFIG_TDP_LEVEL2   0x0000064A

Package. ConfigTDP Level 2 ratio and power level (R/O).

Parameters

ECX	MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.

Example usage

MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);

Note

MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.

#define MSR_HASWELL_CONFIG_TDP_NOMINAL   0x00000648

Package. Base TDP Ratio (R/O).

Parameters

ECX	MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.

Example usage

MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);

Note

MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.

#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS   0x00000690

Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency refers to processor core frequency).

Parameters

ECX	MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.

Example usage

MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);
AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);

Note

MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.

#define MSR_HASWELL_DRAM_ENERGY_STATUS   0x00000619

Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);

Note

MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.

#define MSR_HASWELL_DRAM_PERF_STATUS   0x0000061B

Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);

Note

MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.

#define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS   0x000006B0

Package. Indicator of Frequency Clipping in the Processor Graphics (R/W) (frequency refers to processor graphics frequency).

Parameters

ECX	MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.

Example usage

MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);
AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);

Note

MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.

#define MSR_HASWELL_IA32_PERFEVTSEL0   0x00000186

Thread. Performance Event Select for Counter n (R/W) Supports all fields described inTable 2-2 and the fields below.

Parameters

ECX	MSR_HASWELL_IA32_PERFEVTSELn
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.

Example usage

MSR_HASWELL_IA32_PERFEVTSEL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);
AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);

Note

MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.

#define MSR_HASWELL_IA32_PERFEVTSEL1   0x00000187

Thread. Performance Event Select for Counter n (R/W) Supports all fields described inTable 2-2 and the fields below.

Parameters

ECX	MSR_HASWELL_IA32_PERFEVTSELn
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.

Example usage

MSR_HASWELL_IA32_PERFEVTSEL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);
AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);

Note

MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.

#define MSR_HASWELL_IA32_PERFEVTSEL2   0x00000188

Thread. Performance Event Select for Counter 2 (R/W) Supports all fields described inTable 2-2 and the fields below.

Parameters

ECX	MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.

Example usage

MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);
AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);

Note

MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.

#define MSR_HASWELL_IA32_PERFEVTSEL3   0x00000189

Thread. Performance Event Select for Counter n (R/W) Supports all fields described inTable 2-2 and the fields below.

Parameters

ECX	MSR_HASWELL_IA32_PERFEVTSELn
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.

Example usage

MSR_HASWELL_IA32_PERFEVTSEL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);
AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);

Note

MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.

#define MSR_HASWELL_LBR_SELECT   0x000001C8

Thread. Last Branch Record Filtering Select Register (R/W).

Parameters

ECX	MSR_HASWELL_LBR_SELECT (0x000001C8)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.

Example usage

MSR_HASWELL_LBR_SELECT_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);
AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);

Note

MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.

#define MSR_HASWELL_PKG_C10_RESIDENCY   0x00000632

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States.

Parameters

ECX	MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.

Example usage

MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);
AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);

Note

MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.

#define MSR_HASWELL_PKG_C8_RESIDENCY   0x00000630

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States.

Parameters

ECX	MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.

Example usage

MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);
AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);

Note

MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.

#define MSR_HASWELL_PKG_C9_RESIDENCY   0x00000631

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States.

Parameters

ECX	MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.

Example usage

MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);
AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);

Note

MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.

#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL   0x000000E2

Core. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI Cstates. See http://biosbits.org. <http://biosbits.org>__.

Parameters

ECX	MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.

Example usage

MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);

Note

MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.

#define MSR_HASWELL_PKG_PERF_STATUS   0x00000613

Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".

Parameters

ECX	MSR_HASWELL_PKG_PERF_STATUS (0x00000613)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);

Note

MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.

#define MSR_HASWELL_PKGC_IRTL1   0x0000060B

Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines the interrupt response time limit used by the processor to manage transition to package C6 or C7 state. The latency programmed in this register is for the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States.

Parameters

ECX	MSR_HASWELL_PKGC_IRTL1 (0x0000060B)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.

Example usage

MSR_HASWELL_PKGC_IRTL1_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);
AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);

Note

MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.

#define MSR_HASWELL_PKGC_IRTL2   0x0000060C

Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines the interrupt response time limit used by the processor to manage transition to package C6 or C7 state. The latency programmed in this register is for the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States.

Parameters

ECX	MSR_HASWELL_PKGC_IRTL2 (0x0000060C)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.

Example usage

MSR_HASWELL_PKGC_IRTL2_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);
AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);

Note

MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.

#define MSR_HASWELL_PLATFORM_INFO   0x000000CE

Package.

Parameters

ECX	MSR_HASWELL_PLATFORM_INFO (0x000000CE)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.

Example usage

MSR_HASWELL_PLATFORM_INFO_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);
AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);

Note

MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.

#define MSR_HASWELL_PP0_ENERGY_STATUS   0x00000639

Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters

ECX	MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);

Note

MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.

#define MSR_HASWELL_PP1_ENERGY_STATUS   0x00000641

Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters

ECX	MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);

Note

MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.

#define MSR_HASWELL_PP1_POLICY   0x00000642

Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters

ECX	MSR_HASWELL_PP1_POLICY (0x00000642)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);
AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);

Note

MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.

#define MSR_HASWELL_PP1_POWER_LIMIT   0x00000640

Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

Parameters

ECX	MSR_HASWELL_PP1_POWER_LIMIT (0x00000640)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);
AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);

Note

MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.

#define MSR_HASWELL_RAPL_POWER_UNIT   0x00000606

Package. Unit Multipliers used in RAPL Interfaces (R/O).

Parameters

ECX	MSR_HASWELL_RAPL_POWER_UNIT (0x00000606)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.

Example usage

MSR_HASWELL_RAPL_POWER_UNIT_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);

Note

MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.

#define MSR_HASWELL_RING_PERF_LIMIT_REASONS   0x000006B1

Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W) (frequency refers to ring interconnect in the uncore).

Parameters

ECX	MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.

Example usage

MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);
AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);

Note

MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.

#define MSR_HASWELL_SMM_BLOCKED   0x000004E3

Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical processors in the package. Available only while in SMM.

[Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical processor of its blocked state to service an SMI. The corresponding bit will be set if the logical processor is in one of the following states: Wait For SIPI or SENTER Sleep. The reset value of this field is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be updated.

[Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical processor of its blocked state to service an SMI. The corresponding bit will be set if the logical processor is in one of the following states: Wait For SIPI or SENTER Sleep. The reset value of this field is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be updated.

Parameters

ECX	MSR_HASWELL_SMM_BLOCKED (0x000004E3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);

Note

MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.

#define MSR_HASWELL_SMM_DELAYED   0x000004E2

Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical processors in the package. Available only while in SMM and MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.

[Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical processor of its state in a long flow of internal operation which delays servicing an interrupt. The corresponding bit will be set at the start of long events such as: Microcode Update Load, C6, WBINVD, Ratio Change, Throttle. The bit is automatically cleared at the end of each long event. The reset value of this field is 0. Only bit positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be updated.

[Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical processor of its state in a long flow of internal operation which delays servicing an interrupt. The corresponding bit will be set at the start of long events such as: Microcode Update Load, C6, WBINVD, Ratio Change, Throttle. The bit is automatically cleared at the end of each long event. The reset value of this field is 0. Only bit positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be updated.

Parameters

ECX	MSR_HASWELL_SMM_DELAYED (0x000004E2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);

Note

MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.

#define MSR_HASWELL_SMM_FEATURE_CONTROL   0x000004E0

Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability Enhancement. Accessible only while in SMM.

Parameters

ECX	MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.

Example usage

MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);
AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);

Note

MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.

#define MSR_HASWELL_SMM_MCA_CAP   0x0000017D

THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM.

Parameters

ECX	MSR_HASWELL_SMM_MCA_CAP (0x0000017D)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.

Example usage

MSR_HASWELL_SMM_MCA_CAP_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);
AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);

Note

MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.

#define MSR_HASWELL_TURBO_ACTIVATION_RATIO   0x0000064C

Package. ConfigTDP Control (R/W).

Parameters

ECX	MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.

Example usage

MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);
AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);

Note

MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.

#define MSR_HASWELL_TURBO_RATIO_LIMIT   0x000001AD

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters

ECX	MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.

Example usage

MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);

Note

MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.

#define MSR_HASWELL_UNC_ARB_PERFCTR0   0x000003B0

Package. Uncore Arb unit, performance counter 0.

Parameters

ECX	MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);
AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);

Note

MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.

#define MSR_HASWELL_UNC_ARB_PERFCTR1   0x000003B1

Package. Uncore Arb unit, performance counter 1.

Parameters

ECX	MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);
AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);

Note

MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.

#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0   0x000003B2

Package. Uncore Arb unit, counter 0 event select MSR.

Parameters

ECX	MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);
AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);

Note

MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.

#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1   0x000003B3

Package. Uncore Arb unit, counter 1 event select MSR.

Parameters

ECX	MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);
AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);

Note

MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.

#define MSR_HASWELL_UNC_CBO_0_PERFCTR0   0x00000706

Package. Uncore C-Box 0, performance counter 0.

Parameters

ECX	MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);

Note

MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.

#define MSR_HASWELL_UNC_CBO_0_PERFCTR1   0x00000707

Package. Uncore C-Box 0, performance counter 1.

Parameters

ECX	MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);

Note

MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.

#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0   0x00000700

Package. Uncore C-Box 0, counter 0 event select MSR.

Parameters

ECX	MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);

Note

MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.

#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1   0x00000701

Package. Uncore C-Box 0, counter 1 event select MSR.

Parameters

ECX	MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);

Note

MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.

#define MSR_HASWELL_UNC_CBO_1_PERFCTR0   0x00000716

Package. Uncore C-Box 1, performance counter 0.

Parameters

ECX	MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);

Note

MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.

#define MSR_HASWELL_UNC_CBO_1_PERFCTR1   0x00000717

Package. Uncore C-Box 1, performance counter 1.

Parameters

ECX	MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);

Note

MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.

#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0   0x00000710

Package. Uncore C-Box 1, counter 0 event select MSR.

Parameters

ECX	MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);

Note

MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.

#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1   0x00000711

Package. Uncore C-Box 1, counter 1 event select MSR.

Parameters

ECX	MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);

Note

MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.

#define MSR_HASWELL_UNC_CBO_2_PERFCTR0   0x00000726

Package. Uncore C-Box 2, performance counter 0.

Parameters

ECX	MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);

Note

MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.

#define MSR_HASWELL_UNC_CBO_2_PERFCTR1   0x00000727

Package. Uncore C-Box 2, performance counter 1.

Parameters

ECX	MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);

Note

MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.

#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0   0x00000720

Package. Uncore C-Box 2, counter 0 event select MSR.

Parameters

ECX	MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);

Note

MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.

#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1   0x00000721

Package. Uncore C-Box 2, counter 1 event select MSR.

Parameters

ECX	MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);

Note

MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.

#define MSR_HASWELL_UNC_CBO_3_PERFCTR0   0x00000736

Package. Uncore C-Box 3, performance counter 0.

Parameters

ECX	MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);

Note

MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.

#define MSR_HASWELL_UNC_CBO_3_PERFCTR1   0x00000737

Package. Uncore C-Box 3, performance counter 1.

Parameters

ECX	MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);

Note

MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.

#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0   0x00000730

Package. Uncore C-Box 3, counter 0 event select MSR.

Parameters

ECX	MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);

Note

MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.

#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1   0x00000731

Package. Uncore C-Box 3, counter 1 event select MSR.

Parameters

ECX	MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);
AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);

Note

MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.

#define MSR_HASWELL_UNC_CBO_CONFIG   0x00000396

Package. Uncore C-Box configuration information (R/O).

Parameters

ECX	MSR_HASWELL_UNC_CBO_CONFIG (0x00000396)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.

Example usage

MSR_HASWELL_UNC_CBO_CONFIG_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);

Note

MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.

#define MSR_HASWELL_UNC_PERF_FIXED_CTR   0x00000395

Package. Uncore fixed counter.

Parameters

ECX	MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.

Example usage

MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);
AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);

Note

MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.

#define MSR_HASWELL_UNC_PERF_FIXED_CTRL   0x00000394

Package. Uncore fixed counter control (R/W).

Parameters

ECX	MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.

Example usage

MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);
AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);

Note

MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.

#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL   0x00000391

Package. Uncore PMU global control.

Parameters

ECX	MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.

Example usage

MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);
AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);

Note

MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.

#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS   0x00000392

Package. Uncore PMU main status.

Parameters

ECX	MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.

Example usage

MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);
AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);

Note

MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.