CoreMsr.h File Reference

Data Structures
union	MSR_CORE_EBL_CR_POWERON_REGISTER
union	MSR_CORE_FSB_FREQ_REGISTER
union	MSR_CORE_BBL_CR_CTL3_REGISTER
union	MSR_CORE_THERM2_CTL_REGISTER
union	MSR_CORE_IA32_MISC_ENABLE_REGISTER
union	MSR_CORE_IA32_EFER_REGISTER

Macros
#define	IS_CORE_PROCESSOR(DisplayFamily, DisplayModel)
#define	MSR_CORE_P5_MC_ADDR   0x00000000
#define	MSR_CORE_P5_MC_TYPE   0x00000001
#define	MSR_CORE_EBL_CR_POWERON   0x0000002A
#define	MSR_CORE_FSB_FREQ   0x000000CD
#define	MSR_CORE_BBL_CR_CTL3   0x0000011E
#define	MSR_CORE_THERM2_CTL   0x0000019D
#define	MSR_CORE_IA32_MISC_ENABLE   0x000001A0
#define	MSR_CORE_LASTBRANCH_TOS   0x000001C9
#define	MSR_CORE_LER_FROM_LIP   0x000001DD
#define	MSR_CORE_LER_TO_LIP   0x000001DE
#define	MSR_CORE_MTRRFIX64K_00000   0x00000250
#define	MSR_CORE_MTRRFIX16K_80000   0x00000258
#define	MSR_CORE_MTRRFIX16K_A0000   0x00000259
#define	MSR_CORE_MTRRFIX4K_C0000   0x00000268
#define	MSR_CORE_MTRRFIX4K_C8000   0x00000269
#define	MSR_CORE_MTRRFIX4K_D0000   0x0000026A
#define	MSR_CORE_MTRRFIX4K_D8000   0x0000026B
#define	MSR_CORE_MTRRFIX4K_E0000   0x0000026C
#define	MSR_CORE_MTRRFIX4K_E8000   0x0000026D
#define	MSR_CORE_MTRRFIX4K_F0000   0x0000026E
#define	MSR_CORE_MTRRFIX4K_F8000   0x0000026F
#define	MSR_CORE_MC4_CTL   0x0000040C
#define	MSR_CORE_MC4_STATUS   0x0000040D
#define	MSR_CORE_MC4_ADDR   0x0000040E
#define	MSR_CORE_MC3_ADDR   0x00000412
#define	MSR_CORE_MC3_MISC   0x00000413
#define	MSR_CORE_MC5_CTL   0x00000414
#define	MSR_CORE_MC5_STATUS   0x00000415
#define	MSR_CORE_MC5_ADDR   0x00000416
#define	MSR_CORE_MC5_MISC   0x00000417
#define	MSR_CORE_IA32_EFER   0xC0000080
#define	MSR_CORE_LASTBRANCH_0   0x00000040
#define	MSR_CORE_LASTBRANCH_1   0x00000041
#define	MSR_CORE_LASTBRANCH_2   0x00000042
#define	MSR_CORE_LASTBRANCH_3   0x00000043
#define	MSR_CORE_LASTBRANCH_4   0x00000044
#define	MSR_CORE_LASTBRANCH_5   0x00000045
#define	MSR_CORE_LASTBRANCH_6   0x00000046
#define	MSR_CORE_LASTBRANCH_7   0x00000047
#define	MSR_CORE_MTRRPHYSBASE0   0x00000200
#define	MSR_CORE_MTRRPHYSBASE1   0x00000202
#define	MSR_CORE_MTRRPHYSBASE2   0x00000204
#define	MSR_CORE_MTRRPHYSBASE3   0x00000206
#define	MSR_CORE_MTRRPHYSBASE4   0x00000208
#define	MSR_CORE_MTRRPHYSBASE5   0x0000020A
#define	MSR_CORE_MTRRPHYSMASK6   0x0000020D
#define	MSR_CORE_MTRRPHYSMASK7   0x0000020F
#define	MSR_CORE_MTRRPHYSMASK0   0x00000201
#define	MSR_CORE_MTRRPHYSMASK1   0x00000203
#define	MSR_CORE_MTRRPHYSMASK2   0x00000205
#define	MSR_CORE_MTRRPHYSMASK3   0x00000207
#define	MSR_CORE_MTRRPHYSMASK4   0x00000209
#define	MSR_CORE_MTRRPHYSMASK5   0x0000020B
#define	MSR_CORE_MTRRPHYSBASE6   0x0000020C
#define	MSR_CORE_MTRRPHYSBASE7   0x0000020E

Detailed Description

MSR Definitions for Intel Core Solo and Intel Core Duo Processors.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:

Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_CORE_PROCESSOR	(		DisplayFamily,
			DisplayModel
	)

Value:

(DisplayFamily == 0x06 && \
   ( \
    DisplayModel == 0x0E \
    ) \
   )

Is Intel Core Solo and Intel Core Duo Processors?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

#define MSR_CORE_BBL_CR_CTL3   0x0000011E

Shared.

Parameters

ECX	MSR_CORE_BBL_CR_CTL3 (0x0000011E)
EAX	Lower 32-bits of MSR value. Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.

Example usage

MSR_CORE_BBL_CR_CTL3_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);
AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);

Note

MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.

#define MSR_CORE_EBL_CR_POWERON   0x0000002A

Shared. Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.

Parameters

ECX	MSR_CORE_EBL_CR_POWERON (0x0000002A)
EAX	Lower 32-bits of MSR value. Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.

Example usage

MSR_CORE_EBL_CR_POWERON_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);

Note

MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.

#define MSR_CORE_FSB_FREQ   0x000000CD

Shared. Scalable Bus Speed (RO) This field indicates the scalable bus clock speed:.

Parameters

ECX	MSR_CORE_FSB_FREQ (0x000000CD)
EAX	Lower 32-bits of MSR value. Described by the type MSR_CORE_FSB_FREQ_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_CORE_FSB_FREQ_REGISTER.

Example usage

MSR_CORE_FSB_FREQ_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);

Note

MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.

#define MSR_CORE_IA32_EFER   0xC0000080

Unique. See Table 2-2.

Parameters

ECX	MSR_CORE_IA32_EFER (0xC0000080)
EAX	Lower 32-bits of MSR value. Described by the type MSR_CORE_IA32_EFER_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_CORE_IA32_EFER_REGISTER.

Example usage

MSR_CORE_IA32_EFER_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);

Note

MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.

#define MSR_CORE_IA32_MISC_ENABLE   0x000001A0

Enable Miscellaneous Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.

Parameters

ECX	MSR_CORE_IA32_MISC_ENABLE (0x000001A0)
EAX	Lower 32-bits of MSR value. Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.

Example usage

MSR_CORE_IA32_MISC_ENABLE_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);

Note

MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.

#define MSR_CORE_LASTBRANCH_0   0x00000040

Unique. Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".

Parameters

ECX	MSR_CORE_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);

Note

MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_CORE_LASTBRANCH_1   0x00000041

Unique. Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".

Parameters

ECX	MSR_CORE_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);

Note

MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_CORE_LASTBRANCH_2   0x00000042

Unique. Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".

Parameters

ECX	MSR_CORE_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);

Note

MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_CORE_LASTBRANCH_3   0x00000043

Unique. Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".

Parameters

ECX	MSR_CORE_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);

Note

MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_CORE_LASTBRANCH_4   0x00000044

Unique. Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".

Parameters

ECX	MSR_CORE_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);

Note

MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_CORE_LASTBRANCH_5   0x00000045

Unique. Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".

Parameters

ECX	MSR_CORE_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);

Note

MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_CORE_LASTBRANCH_6   0x00000046

Unique. Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".

Parameters

ECX	MSR_CORE_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);

Note

MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_CORE_LASTBRANCH_7   0x00000047

Unique. Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".

Parameters

ECX	MSR_CORE_LASTBRANCH_n
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);

Note

MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.

#define MSR_CORE_LASTBRANCH_TOS   0x000001C9

Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP (at 40H).

Parameters

ECX	MSR_CORE_LASTBRANCH_TOS (0x000001C9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);

Note

MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.

#define MSR_CORE_LER_FROM_LIP   0x000001DD

Unique. Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.

Parameters

ECX	MSR_CORE_LER_FROM_LIP (0x000001DD)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);

Note

MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.

#define MSR_CORE_LER_TO_LIP   0x000001DE

Unique. Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.

Parameters

ECX	MSR_CORE_LER_TO_LIP (0x000001DE)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);

Note

MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.

#define MSR_CORE_MC3_ADDR   0x00000412

Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

Parameters

ECX	MSR_CORE_MC3_ADDR (0x00000412)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);
AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);

Note

MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.

#define MSR_CORE_MC3_MISC   0x00000413

Unique.

Parameters

ECX	MSR_CORE_MC3_MISC (0x00000413)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);
AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);

Note

MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.

#define MSR_CORE_MC4_ADDR   0x0000040E

Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

Parameters

ECX	MSR_CORE_MC4_ADDR (0x0000040E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);
AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);

Note

MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.

#define MSR_CORE_MC4_CTL   0x0000040C

Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".

Parameters

ECX	MSR_CORE_MC4_CTL (0x0000040C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);
AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);

Note

MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.

#define MSR_CORE_MC4_STATUS   0x0000040D

Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".

Parameters

ECX	MSR_CORE_MC4_STATUS (0x0000040D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);
AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);

Note

MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.

#define MSR_CORE_MC5_ADDR   0x00000416

Unique.

Parameters

ECX	MSR_CORE_MC5_ADDR (0x00000416)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);
AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);

Note

MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.

#define MSR_CORE_MC5_CTL   0x00000414

Unique.

Parameters

ECX	MSR_CORE_MC5_CTL (0x00000414)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);
AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);

Note

MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.

#define MSR_CORE_MC5_MISC   0x00000417

Unique.

Parameters

ECX	MSR_CORE_MC5_MISC (0x00000417)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);
AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);

Note

MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.

#define MSR_CORE_MC5_STATUS   0x00000415

Unique.

Parameters

ECX	MSR_CORE_MC5_STATUS (0x00000415)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);
AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);

Note

MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.

#define MSR_CORE_MTRRFIX16K_80000   0x00000258

Unique.

Parameters

ECX	MSR_CORE_MTRRFIX16K_80000 (0x00000258)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);
AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);

Note

MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.

#define MSR_CORE_MTRRFIX16K_A0000   0x00000259

Unique.

Parameters

ECX	MSR_CORE_MTRRFIX16K_A0000 (0x00000259)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);
AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);

Note

MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.

#define MSR_CORE_MTRRFIX4K_C0000   0x00000268

Unique.

Parameters

ECX	MSR_CORE_MTRRFIX4K_C0000 (0x00000268)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);

Note

MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.

#define MSR_CORE_MTRRFIX4K_C8000   0x00000269

Unique.

Parameters

ECX	MSR_CORE_MTRRFIX4K_C8000 (0x00000269)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);

Note

MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.

#define MSR_CORE_MTRRFIX4K_D0000   0x0000026A

Unique.

Parameters

ECX	MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);

Note

MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.

#define MSR_CORE_MTRRFIX4K_D8000   0x0000026B

Unique.

Parameters

ECX	MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);

Note

MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.

#define MSR_CORE_MTRRFIX4K_E0000   0x0000026C

Unique.

Parameters

ECX	MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);

Note

MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.

#define MSR_CORE_MTRRFIX4K_E8000   0x0000026D

Unique.

Parameters

ECX	MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);

Note

MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.

#define MSR_CORE_MTRRFIX4K_F0000   0x0000026E

Unique.

Parameters

ECX	MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);

Note

MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.

#define MSR_CORE_MTRRFIX4K_F8000   0x0000026F

Unique.

Parameters

ECX	MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);
AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);

Note

MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.

#define MSR_CORE_MTRRFIX64K_00000   0x00000250

Unique.

Parameters

ECX	MSR_CORE_MTRRFIX64K_00000 (0x00000250)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);
AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);

Note

MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.

#define MSR_CORE_MTRRPHYSBASE0   0x00000200

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);

Note

MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_CORE_MTRRPHYSBASE1   0x00000202

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);

Note

MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_CORE_MTRRPHYSBASE2   0x00000204

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);

Note

MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_CORE_MTRRPHYSBASE3   0x00000206

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);

Note

MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_CORE_MTRRPHYSBASE4   0x00000208

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);

Note

MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_CORE_MTRRPHYSBASE5   0x0000020A

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);

Note

MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_CORE_MTRRPHYSBASE6   0x0000020C

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSMASKn (0x00000201)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);

Note

MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_CORE_MTRRPHYSBASE7   0x0000020E

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSMASKn (0x00000201)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);

Note

MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_CORE_MTRRPHYSMASK0   0x00000201

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSMASKn (0x00000201)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);

Note

MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_CORE_MTRRPHYSMASK1   0x00000203

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSMASKn (0x00000201)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);

Note

MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_CORE_MTRRPHYSMASK2   0x00000205

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSMASKn (0x00000201)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);

Note

MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_CORE_MTRRPHYSMASK3   0x00000207

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSMASKn (0x00000201)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);

Note

MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_CORE_MTRRPHYSMASK4   0x00000209

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSMASKn (0x00000201)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);

Note

MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_CORE_MTRRPHYSMASK5   0x0000020B

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSMASKn (0x00000201)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);

Note

MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.

#define MSR_CORE_MTRRPHYSMASK6   0x0000020D

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);

Note

MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_CORE_MTRRPHYSMASK7   0x0000020F

Unique.

Parameters

ECX	MSR_CORE_MTRRPHYSBASEn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);

Note

MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.

#define MSR_CORE_P5_MC_ADDR   0x00000000

Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.

Parameters

ECX	MSR_CORE_P5_MC_ADDR (0x00000000)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);

Note

MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.

#define MSR_CORE_P5_MC_TYPE   0x00000001

Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.

Parameters

ECX	MSR_CORE_P5_MC_TYPE (0x00000001)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);

Note

MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.

#define MSR_CORE_THERM2_CTL   0x0000019D

Unique.

Parameters

ECX	MSR_CORE_THERM2_CTL (0x0000019D)
EAX	Lower 32-bits of MSR value. Described by the type MSR_CORE_THERM2_CTL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_CORE_THERM2_CTL_REGISTER.

Example usage

MSR_CORE_THERM2_CTL_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);
AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);

Note

MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.