MSR_CORE_BBL_CR_CTL3_REGISTER Union Reference

Data Fields
struct {
UINT32   L2HardwareEnabled:1
UINT32   Reserved1:7
UINT32   L2Enabled:1
UINT32   Reserved2:14
UINT32   L2NotPresent:1
UINT32   Reserved3:8
UINT32   Reserved4:32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_CORE_BBL_CR_CTL3

Field Documentation

struct { ... } MSR_CORE_BBL_CR_CTL3_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE_BBL_CR_CTL3_REGISTER::L2Enabled

[Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 = Disabled (default) Until this bit is set the processor will not respond to the WBINVD instruction or the assertion of the FLUSH# input.

UINT32 MSR_CORE_BBL_CR_CTL3_REGISTER::L2HardwareEnabled

[Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = Indicates if the L2 is hardware-disabled.

UINT32 MSR_CORE_BBL_CR_CTL3_REGISTER::L2NotPresent

[Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.

UINT32 MSR_CORE_BBL_CR_CTL3_REGISTER::Reserved1

UINT32 MSR_CORE_BBL_CR_CTL3_REGISTER::Reserved2

UINT32 MSR_CORE_BBL_CR_CTL3_REGISTER::Reserved3

UINT32 MSR_CORE_BBL_CR_CTL3_REGISTER::Reserved4

UINT32 MSR_CORE_BBL_CR_CTL3_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE_BBL_CR_CTL3_REGISTER::Uint64

All bit fields as a 64-bit value