MSR information returned for MSR index MSR_CORE_THERM2_CTL
struct { ... } MSR_CORE_THERM2_CTL_REGISTER::Bits |
UINT32 MSR_CORE_THERM2_CTL_REGISTER::Reserved1 |
UINT32 MSR_CORE_THERM2_CTL_REGISTER::Reserved2 |
UINT32 MSR_CORE_THERM2_CTL_REGISTER::Reserved3 |
UINT32 MSR_CORE_THERM2_CTL_REGISTER::TM_SELECT |
[Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
UINT32 MSR_CORE_THERM2_CTL_REGISTER::Uint32 |
All bit fields as a 32-bit value
UINT64 MSR_CORE_THERM2_CTL_REGISTER::Uint64 |
All bit fields as a 64-bit value