MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Union Reference

Data Fields
struct {
UINT32   Limit:15
UINT32   Enable:1
UINT32   Reserved1:1
UINT32   Time:7
UINT32   Reserved2:8
UINT32   Reserved3:32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SILVERMONT_PP0_POWER_LIMIT

Field Documentation

struct { ... } MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Enable

[Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

UINT32 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Limit

[Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1 RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.

UINT32 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Reserved1

UINT32 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Reserved2

UINT32 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Reserved3

UINT32 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Time

[Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time duration over which the average power must remain below PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time duration. 0x1: 5 second time duration (Default). 0x2: 10 second time duration. 0x3: 15 second time duration. 0x4: 20 second time duration. 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35 second time duration. 0x8: 40 second time duration. 0x9: 45 second time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.

UINT32 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value