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Data Structures | Macros
SilvermontMsr.h File Reference

Data Structures

union  MSR_SILVERMONT_PLATFORM_ID_REGISTER
 
union  MSR_SILVERMONT_EBL_CR_POWERON_REGISTER
 
union  MSR_SILVERMONT_SMI_COUNT_REGISTER
 
union  MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER
 
union  MSR_SILVERMONT_FSB_FREQ_REGISTER
 
union  MSR_SILVERMONT_PLATFORM_INFO_REGISTER
 
union  MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER
 
union  MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER
 
union  MSR_SILVERMONT_BBL_CR_CTL3_REGISTER
 
union  MSR_SILVERMONT_FEATURE_CONFIG_REGISTER
 
union  MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER
 
union  MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER
 
union  MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER
 
union  MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER
 
union  MSR_SILVERMONT_LBR_SELECT_REGISTER
 
union  MSR_SILVERMONT_PEBS_ENABLE_REGISTER
 
union  MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER
 
union  MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER
 
union  MSR_SILVERMONT_PKG_POWER_INFO_REGISTER
 
union  MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER
 

Macros

#define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel)
 
#define MSR_SILVERMONT_PLATFORM_ID   0x00000017
 
#define MSR_SILVERMONT_EBL_CR_POWERON   0x0000002A
 
#define MSR_SILVERMONT_SMI_COUNT   0x00000034
 
#define MSR_SILVERMONT_IA32_FEATURE_CONTROL   0x0000003A
 
#define MSR_SILVERMONT_FSB_FREQ   0x000000CD
 
#define MSR_SILVERMONT_PLATFORM_INFO   0x000000CE
 
#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL   0x000000E2
 
#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE   0x000000E4
 
#define MSR_SILVERMONT_BBL_CR_CTL3   0x0000011E
 
#define MSR_SILVERMONT_FEATURE_CONFIG   0x0000013C
 
#define MSR_SILVERMONT_IA32_MISC_ENABLE   0x000001A0
 
#define MSR_SILVERMONT_TEMPERATURE_TARGET   0x000001A2
 
#define MSR_SILVERMONT_MISC_FEATURE_CONTROL   0x000001A4
 
#define MSR_SILVERMONT_OFFCORE_RSP_0   0x000001A6
 
#define MSR_SILVERMONT_OFFCORE_RSP_1   0x000001A7
 
#define MSR_SILVERMONT_TURBO_RATIO_LIMIT   0x000001AD
 
#define MSR_SILVERMONT_LBR_SELECT   0x000001C8
 
#define MSR_SILVERMONT_LASTBRANCH_TOS   0x000001C9
 
#define MSR_SILVERMONT_LER_FROM_LIP   0x000001DD
 
#define MSR_SILVERMONT_LER_TO_LIP   0x000001DE
 
#define MSR_SILVERMONT_PEBS_ENABLE   0x000003F1
 
#define MSR_SILVERMONT_PKG_C6_RESIDENCY   0x000003FA
 
#define MSR_SILVERMONT_CORE_C6_RESIDENCY   0x000003FD
 
#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM   0x0000048C
 
#define MSR_SILVERMONT_IA32_VMX_FMFUNC   0x00000491
 
#define MSR_SILVERMONT_CORE_C1_RESIDENCY   0x00000660
 
#define MSR_SILVERMONT_RAPL_POWER_UNIT   0x00000606
 
#define MSR_SILVERMONT_PKG_POWER_LIMIT   0x00000610
 
#define MSR_SILVERMONT_PKG_ENERGY_STATUS   0x00000611
 
#define MSR_SILVERMONT_PP0_ENERGY_STATUS   0x00000639
 
#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG   0x00000668
 
#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG   0x00000669
 
#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER   0x00000664
 
#define MSR_SILVERMONT_PKG_POWER_INFO   0x0000066E
 
#define MSR_SILVERMONT_PP0_POWER_LIMIT   0x00000638
 
#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP   0x00000040
 
#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP   0x00000041
 
#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP   0x00000042
 
#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP   0x00000043
 
#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP   0x00000044
 
#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP   0x00000045
 
#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP   0x00000046
 
#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP   0x00000047
 
#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP   0x00000060
 
#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP   0x00000061
 
#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP   0x00000062
 
#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP   0x00000063
 
#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP   0x00000064
 
#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP   0x00000065
 
#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP   0x00000066
 
#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP   0x00000067
 

Detailed Description

MSR Definitions for Intel processors based on the Silvermont microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_SILVERMONT_PROCESSOR (   DisplayFamily,
  DisplayModel 
)
Value:
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x37 || \
DisplayModel == 0x4A || \
DisplayModel == 0x4D || \
DisplayModel == 0x5A || \
DisplayModel == 0x5D \
) \
)

Is Intel processors based on the Silvermont microarchitecture?

Parameters
DisplayFamilyDisplay Family ID
DisplayModelDisplay Model ID
Return values
TRUEYes, it is.
FALSENo, it isn't.
#define MSR_SILVERMONT_BBL_CR_CTL3   0x0000011E

Module.

Parameters
ECXMSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.

Example usage

MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);
AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);
Note
MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG   0x00000668

Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion policy. Writing a value of 0 disables core level HW demotion policy.

Parameters
ECXMSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);
AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);
Note
MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.
#define MSR_SILVERMONT_CORE_C1_RESIDENCY   0x00000660

Core. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1 Residency Counter. (R/O) Value since last reset that this core is in processor-specific C1 states. Counts at the TSC frequency.

Parameters
ECXMSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);
AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);
Note
MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.
#define MSR_SILVERMONT_CORE_C6_RESIDENCY   0x000003FD

Core. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6 Residency Counter. (R/O) Value since last reset that this core is in processor-specific C6 states. Counts at the TSC Frequency.

Parameters
ECXMSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);
AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);
Note
MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
#define MSR_SILVERMONT_EBL_CR_POWERON   0x0000002A

Module. Processor Hard Power-On Configuration (R/W) Writes ignored.

Parameters
ECXMSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.

Example usage

MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);
AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);
Note
MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
#define MSR_SILVERMONT_FEATURE_CONFIG   0x0000013C

Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.

Parameters
ECXMSR_SILVERMONT_FEATURE_CONFIG (0x0000013C)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.

Example usage

MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);
AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);
Note
MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
#define MSR_SILVERMONT_FSB_FREQ   0x000000CD

Module. Scalable Bus Speed(RO) This field indicates the intended scalable bus clock speed for processors based on Silvermont microarchitecture:.

Parameters
ECXMSR_SILVERMONT_FSB_FREQ (0x000000CD)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.

Example usage

MSR_SILVERMONT_FSB_FREQ_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);
Note
MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
#define MSR_SILVERMONT_IA32_FEATURE_CONTROL   0x0000003A

Core. Control Features in Intel 64 Processor (R/W). See Table 2-2.

Parameters
ECXMSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.

Example usage

MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL);
AsmWriteMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL, Msr.Uint64);
Note
MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
#define MSR_SILVERMONT_IA32_MISC_ENABLE   0x000001A0

Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.

Parameters
ECXMSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.

Example usage

MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);
Note
MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM   0x0000048C

Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.

Parameters
ECXMSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);
Note
MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
#define MSR_SILVERMONT_IA32_VMX_FMFUNC   0x00000491

Core. Capability Reporting Register of VM-Function Controls (R/O) See Table 2-2.

Parameters
ECXMSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);
Note
MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP   0x00000040

Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5 and record format in Section 17.4.8.1.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_FROM_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP   0x00000060

Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_TO_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP   0x00000041

Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5 and record format in Section 17.4.8.1.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_FROM_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP   0x00000061

Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_TO_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP   0x00000042

Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5 and record format in Section 17.4.8.1.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_FROM_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP   0x00000062

Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_TO_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP   0x00000043

Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5 and record format in Section 17.4.8.1.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_FROM_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP   0x00000063

Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_TO_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP   0x00000044

Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5 and record format in Section 17.4.8.1.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_FROM_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP   0x00000064

Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_TO_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP   0x00000045

Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5 and record format in Section 17.4.8.1.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_FROM_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP   0x00000065

Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_TO_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP   0x00000046

Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5 and record format in Section 17.4.8.1.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_FROM_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP   0x00000066

Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_TO_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP   0x00000047

Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5 and record format in Section 17.4.8.1.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_FROM_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP   0x00000067

Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_n_TO_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
#define MSR_SILVERMONT_LASTBRANCH_TOS   0x000001C9

Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP.

Parameters
ECXMSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);
Note
MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
#define MSR_SILVERMONT_LBR_SELECT   0x000001C8

Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2, "Filtering of Last Branch Records.".

Parameters
ECXMSR_SILVERMONT_LBR_SELECT (0x000001C8)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.

Example usage

MSR_SILVERMONT_LBR_SELECT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_LBR_SELECT);
AsmWriteMsr64 (MSR_SILVERMONT_LBR_SELECT, Msr.Uint64);
Note
MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
#define MSR_SILVERMONT_LER_FROM_LIP   0x000001DD

Core. Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.

Parameters
ECXMSR_SILVERMONT_LER_FROM_LIP (0x000001DD)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);
Note
MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
#define MSR_SILVERMONT_LER_TO_LIP   0x000001DE

Core. Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.

Parameters
ECXMSR_SILVERMONT_LER_TO_LIP (0x000001DE)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);
Note
MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG   0x00000669

Package. Module C6 demotion policy config MSR. Controls module (i.e. two cores sharing the second-level cache) C6 demotion policy. Writing a value of 0 disables module level HW demotion policy.

Parameters
ECXMSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);
AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);
Note
MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.
#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER   0x00000664

Module. Module C6 Residency Counter (R/0) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. Time that this module is in module-specific C6 states since last reset. Counts at 1 Mhz frequency.

Parameters
ECXMSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);
Note
MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.
#define MSR_SILVERMONT_MISC_FEATURE_CONTROL   0x000001A4

Miscellaneous Feature Control (R/W).

Parameters
ECXMSR_SILVERMONT_MISC_FEATURE_CONTROL (0x000001A4)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.

Example usage

MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL);
AsmWriteMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL, Msr.Uint64);
Note
MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
#define MSR_SILVERMONT_OFFCORE_RSP_0   0x000001A6

Module. Offcore Response Event Select Register (R/W).

Parameters
ECXMSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);
AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);
Note
MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
#define MSR_SILVERMONT_OFFCORE_RSP_1   0x000001A7

Module. Offcore Response Event Select Register (R/W).

Parameters
ECXMSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);
AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);
Note
MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
#define MSR_SILVERMONT_PEBS_ENABLE   0x000003F1

Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling (PEBS).".

Parameters
ECXMSR_SILVERMONT_PEBS_ENABLE (0x000003F1)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.

Example usage

MSR_SILVERMONT_PEBS_ENABLE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);
AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);
Note
MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
#define MSR_SILVERMONT_PKG_C6_RESIDENCY   0x000003FA

Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C6 states. Counts at the TSC Frequency.

Parameters
ECXMSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);
AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);
Note
MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL   0x000000E2

Module. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. See http://biosbits.org.

Parameters
ECXMSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.

Example usage

MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
Note
MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
#define MSR_SILVERMONT_PKG_ENERGY_STATUS   0x00000611

Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.

Parameters
ECXMSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);
Note
MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
#define MSR_SILVERMONT_PKG_POWER_INFO   0x0000066E

Package. PKG RAPL Parameter (R/0).

Parameters
ECXMSR_SILVERMONT_PKG_POWER_INFO (0x0000066E)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.

Example usage

MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);
Note
MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
#define MSR_SILVERMONT_PKG_POWER_LIMIT   0x00000610

Package. PKG RAPL Power Limit Control (R/W).

Parameters
ECXMSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.

Example usage

MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);
AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);
Note
MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
#define MSR_SILVERMONT_PLATFORM_ID   0x00000017

Module. Model Specific Platform ID (R).

Parameters
ECXMSR_SILVERMONT_PLATFORM_ID (0x00000017)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.

Example usage

MSR_SILVERMONT_PLATFORM_ID_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);
Note
MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
#define MSR_SILVERMONT_PLATFORM_INFO   0x000000CE

Package. Platform Information: Contains power management and other model specific features enumeration. See http://biosbits.org.

Parameters
ECXMSR_SILVERMONT_PLATFORM_INFO (0x000000CE)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.

Example usage

MSR_SILVERMONT_PLATFORM_INFO_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO);
AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);
#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE   0x000000E4

Module. Power Management IO Redirection in C-state (R/W) See http://biosbits.org.

Parameters
ECXMSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.

Example usage

MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);
AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);
Note
MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
#define MSR_SILVERMONT_PP0_ENERGY_STATUS   0x00000639

Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 2-8.

Parameters
ECXMSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);
Note
MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
#define MSR_SILVERMONT_PP0_POWER_LIMIT   0x00000638

Package. PP0 RAPL Power Limit Control (R/W).

Parameters
ECXMSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.

Example usage

MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);
AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);
Note
MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
#define MSR_SILVERMONT_RAPL_POWER_UNIT   0x00000606

Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, "RAPL Interfaces.".

Parameters
ECXMSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.

Example usage

MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);
Note
MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
#define MSR_SILVERMONT_SMI_COUNT   0x00000034

Core. SMI Counter (R/O).

Parameters
ECXMSR_SILVERMONT_SMI_COUNT (0x00000034)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.

Example usage

MSR_SILVERMONT_SMI_COUNT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);
Note
MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
#define MSR_SILVERMONT_TEMPERATURE_TARGET   0x000001A2

Package.

Parameters
ECXMSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.

Example usage

MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);
AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);
Note
MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
#define MSR_SILVERMONT_TURBO_RATIO_LIMIT   0x000001AD

Package. Maximum Ratio Limit of Turbo Mode (RW).

Parameters
ECXMSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD)
EAXLower 32-bits of MSR value. Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.

Example usage

MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);
AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
Note
MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.