MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Union Reference

Data Fields
struct {
UINT32   PCIERatio:2
UINT32   LPLLSelect:1
UINT32   LONGRESET:1
UINT32   Reserved1:28
UINT32   Reserved2:32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_HASWELL_E_PCIE_PLL_RATIO

Field Documentation

struct { ... } MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::LONGRESET

[Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out before re-locking Gen2/Gen3 PLLs.

UINT32 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::LPLLSelect

[Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of PCIE Ratio.

UINT32 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::PCIERatio

[Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz operation.

UINT32 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::Reserved1

UINT32 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::Reserved2

UINT32 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::Uint64

All bit fields as a 64-bit value