Data Structures
union	MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER

union	MSR_HASWELL_E_THREAD_ID_INFO_REGISTER

union	MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER

union	MSR_HASWELL_E_IA32_MCG_CAP_REGISTER

union	MSR_HASWELL_E_SMM_MCA_CAP_REGISTER

union	MSR_HASWELL_E_ERROR_CONTROL_REGISTER

union	MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER

union	MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER

union	MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER

union	MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER

union	MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER

union	MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER

union	MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER

union	MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER

union	MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER

union	MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER

Macros
#define	IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel)

#define	MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035

#define	MSR_HASWELL_E_THREAD_ID_INFO 0x00000053

#define	MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2

#define	MSR_HASWELL_E_IA32_MCG_CAP 0x00000179

#define	MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D

#define	MSR_HASWELL_E_ERROR_CONTROL 0x0000017F

#define	MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD

#define	MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE

#define	MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF

#define	MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606

#define	MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618

#define	MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619

#define	MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B

#define	MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C

#define	MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E

#define	MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620

#define	MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639

#define	MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690

#define	MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D

#define	MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F

#define	MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700

#define	MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701

#define	MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702

#define	MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703

#define	MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704

#define	MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705

#define	MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706

#define	MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708

#define	MSR_HASWELL_E_U_PMON_CTR0 0x00000709

#define	MSR_HASWELL_E_U_PMON_CTR1 0x0000070A

#define	MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710

#define	MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711

#define	MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712

#define	MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713

#define	MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714

#define	MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715

#define	MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716

#define	MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717

#define	MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718

#define	MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719

#define	MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A

#define	MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720

#define	MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721

#define	MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722

#define	MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723

#define	MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724

#define	MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725

#define	MSR_HASWELL_E_S0_PMON_CTR0 0x00000726

#define	MSR_HASWELL_E_S0_PMON_CTR1 0x00000727

#define	MSR_HASWELL_E_S0_PMON_CTR2 0x00000728

#define	MSR_HASWELL_E_S0_PMON_CTR3 0x00000729

#define	MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A

#define	MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B

#define	MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C

#define	MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D

#define	MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E

#define	MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F

#define	MSR_HASWELL_E_S1_PMON_CTR0 0x00000730

#define	MSR_HASWELL_E_S1_PMON_CTR1 0x00000731

#define	MSR_HASWELL_E_S1_PMON_CTR2 0x00000732

#define	MSR_HASWELL_E_S1_PMON_CTR3 0x00000733

#define	MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734

#define	MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735

#define	MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736

#define	MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737

#define	MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738

#define	MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739

#define	MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A

#define	MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B

#define	MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C

#define	MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D

#define	MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E

#define	MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F

#define	MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740

#define	MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741

#define	MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742

#define	MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743

#define	MSR_HASWELL_E_S3_PMON_CTR0 0x00000744

#define	MSR_HASWELL_E_S3_PMON_CTR1 0x00000745

#define	MSR_HASWELL_E_S3_PMON_CTR2 0x00000746

#define	MSR_HASWELL_E_S3_PMON_CTR3 0x00000747

#define	MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00

#define	MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01

#define	MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02

#define	MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03

#define	MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04

#define	MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05

#define	MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06

#define	MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07

#define	MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08

#define	MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09

#define	MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A

#define	MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B

#define	MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10

#define	MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11

#define	MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12

#define	MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13

#define	MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14

#define	MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15

#define	MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16

#define	MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17

#define	MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18

#define	MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19

#define	MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A

#define	MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B

#define	MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20

#define	MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21

#define	MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22

#define	MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23

#define	MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24

#define	MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25

#define	MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26

#define	MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27

#define	MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28

#define	MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29

#define	MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A

#define	MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B

#define	MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30

#define	MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31

#define	MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32

#define	MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33

#define	MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34

#define	MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35

#define	MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36

#define	MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37

#define	MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38

#define	MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39

#define	MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A

#define	MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B

#define	MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40

#define	MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41

#define	MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42

#define	MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43

#define	MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44

#define	MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45

#define	MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46

#define	MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47

#define	MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48

#define	MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49

#define	MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A

#define	MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B

#define	MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50

#define	MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51

#define	MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52

#define	MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53

#define	MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54

#define	MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55

#define	MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56

#define	MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57

#define	MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58

#define	MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59

#define	MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A

#define	MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B

#define	MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60

#define	MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61

#define	MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62

#define	MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63

#define	MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64

#define	MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65

#define	MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66

#define	MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67

#define	MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68

#define	MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69

#define	MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A

#define	MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B

#define	MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70

#define	MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71

#define	MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72

#define	MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73

#define	MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74

#define	MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75

#define	MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76

#define	MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77

#define	MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78

#define	MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79

#define	MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A

#define	MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B

#define	MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80

#define	MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81

#define	MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82

#define	MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83

#define	MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84

#define	MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85

#define	MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86

#define	MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87

#define	MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88

#define	MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89

#define	MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A

#define	MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B

#define	MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90

#define	MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91

#define	MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92

#define	MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93

#define	MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94

#define	MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95

#define	MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96

#define	MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97

#define	MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98

#define	MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99

#define	MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A

#define	MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B

#define	MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0

#define	MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1

#define	MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2

#define	MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3

#define	MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4

#define	MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5

#define	MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6

#define	MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7

#define	MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8

#define	MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9

#define	MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA

#define	MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB

#define	MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0

#define	MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1

#define	MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2

#define	MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3

#define	MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4

#define	MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5

#define	MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6

#define	MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7

#define	MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8

#define	MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9

#define	MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA

#define	MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB

#define	MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0

#define	MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1

#define	MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2

#define	MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3

#define	MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4

#define	MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5

#define	MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6

#define	MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7

#define	MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8

#define	MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9

#define	MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA

#define	MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB

#define	MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0

#define	MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1

#define	MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2

#define	MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3

#define	MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4

#define	MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5

#define	MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6

#define	MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7

#define	MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8

#define	MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9

#define	MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA

#define	MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB

#define	MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0

#define	MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1

#define	MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2

#define	MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3

#define	MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4

#define	MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5

#define	MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6

#define	MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7

#define	MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8

#define	MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9

#define	MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA

#define	MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB

#define	MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0

#define	MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1

#define	MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2

#define	MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3

#define	MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4

#define	MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5

#define	MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6

#define	MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7

#define	MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8

#define	MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9

#define	MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA

#define	MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB

#define	MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00

#define	MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01

#define	MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02

#define	MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03

#define	MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04

#define	MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05

#define	MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06

#define	MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07

#define	MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08

#define	MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09

#define	MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A

#define	MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B

#define	MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10

#define	MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11

#define	MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12

#define	MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13

#define	MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14

#define	MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15

#define	MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16

#define	MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17


#define	MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18

#define	MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19

#define	MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A

#define	MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B

Detailed Description

MSR Definitions for Intel processors based on the Haswell-E microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_HASWELL_E_PROCESSOR	(	DisplayFamily,
		DisplayModel
	)

Value:

(DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x3F    \
    )                       \
   )

Is Intel processors based on the Haswell-E microarchitecture?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

#define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00

Package. Uncore C-box 0 perfmon for box-wide control.

Parameters

ECX	MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05

Package. Uncore C-box 0 perfmon box wide filter 0.

Parameters

ECX	MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06

Package. Uncore C-box 0 perfmon box wide filter 1.

Parameters

ECX	MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07

Package. Uncore C-box 0 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08

Package. Uncore C-box 0 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09

Package. Uncore C-box 0 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A

Package. Uncore C-box 0 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B

Package. Uncore C-box 0 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01

Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.

Parameters

ECX	MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02

Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.

Parameters

ECX	MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03

Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.

Parameters

ECX	MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04

Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.

Parameters

ECX	MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0

Package. Uncore C-box 10 perfmon local box wide control.

Parameters

ECX	MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5

Package. Uncore C-box 10 perfmon box wide filter0.

Parameters

ECX	MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6

Package. Uncore C-box 10 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7

Package. Uncore C-box 10 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8

Package. Uncore C-box 10 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9

Package. Uncore C-box 10 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA

Package. Uncore C-box 10 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB

Package. Uncore C-box 10 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1

Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.

Parameters

ECX	MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2

Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.

Parameters

ECX	MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3

Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.

Parameters

ECX	MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4

Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.

Parameters

ECX	MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0

Package. Uncore C-box 11 perfmon local box wide control.

Parameters

ECX	MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5

Package. Uncore C-box 11 perfmon box wide filter0.

Parameters

ECX	MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6

Package. Uncore C-box 11 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7

Package. Uncore C-box 11 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8

Package. Uncore C-box 11 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9

Package. Uncore C-box 11 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA

Package. Uncore C-box 11 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB

Package. Uncore C-box 11 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1

Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.

Parameters

ECX	MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2

Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.

Parameters

ECX	MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3

Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.

Parameters

ECX	MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4

Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.

Parameters

ECX	MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0

Package. Uncore C-box 12 perfmon local box wide control.

Parameters

ECX	MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5

Package. Uncore C-box 12 perfmon box wide filter0.

Parameters

ECX	MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6

Package. Uncore C-box 12 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7

Package. Uncore C-box 12 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8

Package. Uncore C-box 12 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9

Package. Uncore C-box 12 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA

Package. Uncore C-box 12 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB

Package. Uncore C-box 12 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1

Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.

Parameters

ECX	MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2

Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.

Parameters

ECX	MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3

Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.

Parameters

ECX	MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4

Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.

Parameters

ECX	MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0

Package. Uncore C-box 13 perfmon local box wide control.

Parameters

ECX	MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5

Package. Uncore C-box 13 perfmon box wide filter0.

Parameters

ECX	MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6

Package. Uncore C-box 13 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7

Package. Uncore C-box 13 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8

Package. Uncore C-box 13 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9

Package. Uncore C-box 13 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA

Package. Uncore C-box 13 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB

Package. Uncore C-box 13 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1

Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.

Parameters

ECX	MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2

Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.

Parameters

ECX	MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3

Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.

Parameters

ECX	MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4

Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.

Parameters

ECX	MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0

Package. Uncore C-box 14 perfmon local box wide control.

Parameters

ECX	MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5

Package. Uncore C-box 14 perfmon box wide filter0.

Parameters

ECX	MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);

Note: MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.

#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6

Package. Uncore C-box 14 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7

Package. Uncore C-box 14 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8

Package. Uncore C-box 14 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9

Package. Uncore C-box 14 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA

Package. Uncore C-box 14 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB

Package. Uncore C-box 14 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1

Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.

Parameters

ECX	MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2

Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.

Parameters

ECX	MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3

Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.

Parameters

ECX	MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4

Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.

Parameters

ECX	MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0

Package. Uncore C-box 15 perfmon local box wide control.

Parameters

ECX	MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5

Package. Uncore C-box 15 perfmon box wide filter0.

Parameters

ECX	MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6

Package. Uncore C-box 15 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7

Package. Uncore C-box 15 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8

Package. Uncore C-box 15 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9

Package. Uncore C-box 15 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA

Package. Uncore C-box 15 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB

Package. Uncore C-box 15 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1

Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.

Parameters

ECX	MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2

Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.

Parameters

ECX	MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3

Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.

Parameters

ECX	MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4

Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.

Parameters

ECX	MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00

Package. Uncore C-box 16 perfmon for box-wide control.

Parameters

ECX	MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05

Package. Uncore C-box 16 perfmon box wide filter 0.

Parameters

ECX	MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06

Package. Uncore C-box 16 perfmon box wide filter 1.

Parameters

ECX	MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07

Package. Uncore C-box 16 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08

Package. Uncore C-box 16 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09

Package. Uncore C-box 16 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A

Package. Uncore C-box 16 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B

Package. Uncore C-box 16 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01

Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.

Parameters

ECX	MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02

Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.

Parameters

ECX	MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03

Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.

Parameters

ECX	MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04

Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.

Parameters

ECX	MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10

Package. Uncore C-box 17 perfmon for box-wide control.

Parameters

ECX	MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15

Package. Uncore C-box 17 perfmon box wide filter 0.

Parameters

ECX	MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16

Package. Uncore C-box 17 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17

Package. Uncore C-box 17 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18

Package. Uncore C-box 17 perfmon counter n.

Parameters

ECX	MSR_HASWELL_E_C17_PMON_CTRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM. MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM. MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM. MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19

Package. Uncore C-box 17 perfmon counter n.

Parameters

ECX	MSR_HASWELL_E_C17_PMON_CTRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM. MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM. MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM. MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A

Package. Uncore C-box 17 perfmon counter n.

Parameters

ECX	MSR_HASWELL_E_C17_PMON_CTRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM. MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM. MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM. MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B

Package. Uncore C-box 17 perfmon counter n.

Parameters

ECX	MSR_HASWELL_E_C17_PMON_CTRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM. MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM. MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM. MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11

Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.

Parameters

ECX	MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12

Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.

Parameters

ECX	MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13

Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.

Parameters

ECX	MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14

Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.

Parameters

ECX	MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10

Package. Uncore C-box 1 perfmon for box-wide control.

Parameters

ECX	MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15

Package. Uncore C-box 1 perfmon box wide filter 0.

Parameters

ECX	MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16

Package. Uncore C-box 1 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17

Package. Uncore C-box 1 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18

Package. Uncore C-box 1 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19

Package. Uncore C-box 1 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A

Package. Uncore C-box 1 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B

Package. Uncore C-box 1 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11

Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.

Parameters

ECX	MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12

Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.

Parameters

ECX	MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13

Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.

Parameters

ECX	MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14

Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.

Parameters

ECX	MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20

Package. Uncore C-box 2 perfmon for box-wide control.

Parameters

ECX	MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25

Package. Uncore C-box 2 perfmon box wide filter 0.

Parameters

ECX	MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26

Package. Uncore C-box 2 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27

Package. Uncore C-box 2 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28

Package. Uncore C-box 2 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29

Package. Uncore C-box 2 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A

Package. Uncore C-box 2 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B

Package. Uncore C-box 2 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21

Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.

Parameters

ECX	MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22

Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.

Parameters

ECX	MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23

Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.

Parameters

ECX	MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24

Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.

Parameters

ECX	MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30

Package. Uncore C-box 3 perfmon for box-wide control.

Parameters

ECX	MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35

Package. Uncore C-box 3 perfmon box wide filter 0.

Parameters

ECX	MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36

Package. Uncore C-box 3 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37

Package. Uncore C-box 3 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38

Package. Uncore C-box 3 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39

Package. Uncore C-box 3 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A

Package. Uncore C-box 3 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B

Package. Uncore C-box 3 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31

Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.

Parameters

ECX	MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32

Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.

Parameters

ECX	MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33

Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.

Parameters

ECX	MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34

Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.

Parameters

ECX	MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40

Package. Uncore C-box 4 perfmon for box-wide control.

Parameters

ECX	MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45

Package. Uncore C-box 4 perfmon box wide filter 0.

Parameters

ECX	MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46

Package. Uncore C-box 4 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47

Package. Uncore C-box 4 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48

Package. Uncore C-box 4 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49

Package. Uncore C-box 4 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A

Package. Uncore C-box 4 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B

Package. Uncore C-box 4 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41

Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.

Parameters

ECX	MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42

Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.

Parameters

ECX	MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43

Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.

Parameters

ECX	MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44

Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.

Parameters

ECX	MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50

Package. Uncore C-box 5 perfmon for box-wide control.

Parameters

ECX	MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55

Package. Uncore C-box 5 perfmon box wide filter 0.

Parameters

ECX	MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56

Package. Uncore C-box 5 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57

Package. Uncore C-box 5 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58

Package. Uncore C-box 5 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59

Package. Uncore C-box 5 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A

Package. Uncore C-box 5 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B

Package. Uncore C-box 5 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51

Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.

Parameters

ECX	MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52

Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.

Parameters

ECX	MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53

Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.

Parameters

ECX	MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54

Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.

Parameters

ECX	MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60

Package. Uncore C-box 6 perfmon for box-wide control.

Parameters

ECX	MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65

Package. Uncore C-box 6 perfmon box wide filter 0.

Parameters

ECX	MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66

Package. Uncore C-box 6 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67

Package. Uncore C-box 6 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68

Package. Uncore C-box 6 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69

Package. Uncore C-box 6 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A

Package. Uncore C-box 6 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B

Package. Uncore C-box 6 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61

Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.

Parameters

ECX	MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62

Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.

Parameters

ECX	MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63

Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.

Parameters

ECX	MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64

Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.

Parameters

ECX	MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70

Package. Uncore C-box 7 perfmon for box-wide control.

Parameters

ECX	MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75

Package. Uncore C-box 7 perfmon box wide filter 0.

Parameters

ECX	MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76

Package. Uncore C-box 7 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77

Package. Uncore C-box 7 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78

Package. Uncore C-box 7 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79

Package. Uncore C-box 7 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A

Package. Uncore C-box 7 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B

Package. Uncore C-box 7 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71

Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.

Parameters

ECX	MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72

Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.

Parameters

ECX	MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73

Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.

Parameters

ECX	MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74

Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.

Parameters

ECX	MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80

Package. Uncore C-box 8 perfmon local box wide control.

Parameters

ECX	MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85

Package. Uncore C-box 8 perfmon box wide filter0.

Parameters

ECX	MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86

Package. Uncore C-box 8 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87

Package. Uncore C-box 8 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88

Package. Uncore C-box 8 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89

Package. Uncore C-box 8 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A

Package. Uncore C-box 8 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B

Package. Uncore C-box 8 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81

Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.

Parameters

ECX	MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82

Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.

Parameters

ECX	MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83

Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.

Parameters

ECX	MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84

Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.

Parameters

ECX	MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90

Package. Uncore C-box 9 perfmon local box wide control.

Parameters

ECX	MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95

Package. Uncore C-box 9 perfmon box wide filter0.

Parameters

ECX	MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);

Note: MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.

#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96

Package. Uncore C-box 9 perfmon box wide filter1.

Parameters

ECX	MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);

Note: MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.

#define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97

Package. Uncore C-box 9 perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98

Package. Uncore C-box 9 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99

Package. Uncore C-box 9 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A

Package. Uncore C-box 9 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B

Package. Uncore C-box 9 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91

Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.

Parameters

ECX	MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92

Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.

Parameters

ECX	MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93

Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.

Parameters

ECX	MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94

Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.

Parameters

ECX	MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690

Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency refers to processor core frequency).

Parameters

ECX	MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.

Example usage

MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);
AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);

Note: MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.

#define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035

Package. Configured State of Enabled Processor Core Count and Logical Processor Count (RO) - After a Power-On RESET, enumerates factory configuration of the number of processor cores and logical processors in the physical package. - Following the sequence of (i) BIOS modified a Configuration Mask which selects a subset of processor cores to be active post RESET and (ii) a RESET event after the modification, enumerates the current configuration of enabled processor core count and logical processor count in the physical package.

Parameters

ECX	MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.

Example usage

MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);

Note: MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.

#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619

Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.

Parameters

ECX	MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.

Example usage

MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);

Note: MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.

#define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B

Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);

Note: MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.

#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C

Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);
AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);

Note: MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.

#define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618

Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL Domain.".

Parameters

ECX	MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);
AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);

Note: MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.

#define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F

Package. MC Bank Error Configuration (R/W).

Parameters

ECX	MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.

Example usage

MSR_HASWELL_E_ERROR_CONTROL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);
AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);

Note: MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.

#define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179

Thread. Global Machine Check Capability (R/O).

Parameters

ECX	MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.

Example usage

MSR_HASWELL_E_IA32_MCG_CAP_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);

Note: MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.

#define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F

THREAD. Resource Association Register (R/W)..

Parameters

ECX	MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.

Example usage

MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);
AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);

Note: MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.

#define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D

THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.

Parameters

ECX	MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.

Example usage

MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);
AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);

Note: MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.

#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620

Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select.

Parameters

ECX	MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.

Example usage

MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);
AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);

#define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E

Package. Configuration of PCIE PLL Relative to BCLK(R/W).

Parameters

ECX	MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.

Example usage

MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);
AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);

Note: MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.

#define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710

Package. Uncore PCU perfmon for PCU-box-wide control.

Parameters

ECX	MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715

Package. Uncore PCU perfmon box-wide filter.

Parameters

ECX	MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);

Note: MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.

#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716

Package. Uncore PCU perfmon box wide status.

Parameters

ECX	MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717

Package. Uncore PCU perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718

Package. Uncore PCU perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719

Package. Uncore PCU perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A

Package. Uncore PCU perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711

Package. Uncore PCU perfmon event select for PCU counter 0.

Parameters

ECX	MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712

Package. Uncore PCU perfmon event select for PCU counter 1.

Parameters

ECX	MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713

Package. Uncore PCU perfmon event select for PCU counter 2.

Parameters

ECX	MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714

Package. Uncore PCU perfmon event select for PCU counter 3.

Parameters

ECX	MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2

Core. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. <http://biosbits.org>__.

Parameters

ECX	MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.

Example usage

MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);

Note: MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.

#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702

Package. Uncore perfmon per-socket global configuration.

Parameters

ECX	MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);
AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);

Note: MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.

#define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700

Package. Uncore perfmon per-socket global control.

Parameters

ECX	MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);

Note: MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.

#define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701

Package. Uncore perfmon per-socket global status.

Parameters

ECX	MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);

Note: MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.

#define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639

Package. Reserved (R/O) Reads return 0.

Parameters

ECX	MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);

Note: MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.

#define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606

Package. Unit Multipliers used in RAPL Interfaces (R/O).

Parameters

ECX	MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.

Example usage

MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);

Note: MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.

#define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720

Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.

Parameters

ECX	MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725

Package. Uncore SBo 0 perfmon box-wide filter.

Parameters

ECX	MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);

Note: MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.

#define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726

Package. Uncore SBo 0 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727

Package. Uncore SBo 0 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728

Package. Uncore SBo 0 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729

Package. Uncore SBo 0 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721

Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.

Parameters

ECX	MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722

Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.

Parameters

ECX	MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723

Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.

Parameters

ECX	MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724

Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.

Parameters

ECX	MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A

Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.

Parameters

ECX	MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F

Package. Uncore SBo 1 perfmon box-wide filter.

Parameters

ECX	MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);

Note: MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.

#define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730

Package. Uncore SBo 1 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731

Package. Uncore SBo 1 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732

Package. Uncore SBo 1 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733

Package. Uncore SBo 1 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B

Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.

Parameters

ECX	MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C

Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.

Parameters

ECX	MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D

Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.

Parameters

ECX	MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E

Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.

Parameters

ECX	MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734

Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.

Parameters

ECX	MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739

Package. Uncore SBo 2 perfmon box-wide filter.

Parameters

ECX	MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);

Note: MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.

#define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A

Package. Uncore SBo 2 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B

Package. Uncore SBo 2 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C

Package. Uncore SBo 2 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D

Package. Uncore SBo 2 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735

Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.

Parameters

ECX	MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736

Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.

Parameters

ECX	MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737

Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.

Parameters

ECX	MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738

Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.

Parameters

ECX	MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E

Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.

Parameters

ECX	MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);

Note: MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.

#define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743

Package. Uncore SBo 3 perfmon box-wide filter.

Parameters

ECX	MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);

Note: MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.

#define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744

Package. Uncore SBo 3 perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745

Package. Uncore SBo 3 perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746

Package. Uncore SBo 3 perfmon counter 2.

Parameters

ECX	MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);

Note: MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.

#define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747

Package. Uncore SBo 3 perfmon counter 3.

Parameters

ECX	MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);

Note: MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.

#define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F

Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.

Parameters

ECX	MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740

Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.

Parameters

ECX	MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741

Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.

Parameters

ECX	MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);

Note: MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.

#define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742

Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.

Parameters

ECX	MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);
AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);

Note: MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.

#define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D

THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM.

Parameters

ECX	MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.

Example usage

MSR_HASWELL_E_SMM_MCA_CAP_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);
AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);

Note: MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.

#define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053

Thread. A Hardware Assigned ID for the Logical Processor (RO).

Parameters

ECX	MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.

Example usage

MSR_HASWELL_E_THREAD_ID_INFO_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);

Note: MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.

#define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters

ECX	MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.

Example usage

MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);

Note: MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.

#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters

ECX	MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.

Example usage

MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);

Note: MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.

#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters

ECX	MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)
EAX	Lower 32-bits of MSR value. Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.

Example usage

MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER  Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);

Note: MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.

#define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708

Package. Uncore U-box perfmon U-box wide status.

Parameters

ECX	MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);

Note: MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.

#define MSR_HASWELL_E_U_PMON_CTR0 0x00000709

Package. Uncore U-box perfmon counter 0.

Parameters

ECX	MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);

Note: MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.

#define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A

Package. Uncore U-box perfmon counter 1.

Parameters

ECX	MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);

Note: MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.

#define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705

Package. Uncore U-box perfmon event select for U-box counter 0.

Parameters

ECX	MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);

Note: MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.

#define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706

Package. Uncore U-box perfmon event select for U-box counter 1.

Parameters

ECX	MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);

Note: MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.

#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703

Package. Uncore U-box UCLK fixed counter control.

Parameters

ECX	MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);

Note: MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.

#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704

Package. Uncore U-box UCLK fixed counter.

Parameters

ECX	MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;
Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);
AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);

Note: MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.

Data Structures

Macros

Detailed Description

Macro Definition Documentation