MSR information returned for MSR index MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS
| struct { ... } MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::Bits |
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::CorePowerLimitingLog |
[Bit 25] Core Power Limiting Log When set, indicates that the Core Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointLog |
[Bit 28] Electrical Design Point Log When set, indicates that the EDP Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointStatus |
[Bit 12] Electrical Design Point Status (R0) When set, frequency is reduced below the operating system request due to electrical design point constraints (e.g. maximum electrical current consumption).
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::MaximumEfficiencyFrequencyLog |
[Bit 30] Maximum Efficiency Frequency Log When set, indicates that the Maximum Efficiency Frequency Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::MaximumEfficiencyFrequencyStatus |
[Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency is reduced below the maximum efficiency frequency.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::MaxTurboLimitLog |
[Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo Limit Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::MaxTurboLimitStatus |
[Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced below the operating system request due to multi-core turbo limits.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PL1Log |
[Bit 18] Package-Level PL1 Power Limiting Log When set, indicates that the Package Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PL1Status |
[Bit 2] Package-Level Power Limiting PL1 Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL1.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PL2Log |
[Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that the Package Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PL2Status |
[Bit 3] Package-Level PL2 Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL2.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PowerLimitingStatus |
[Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to domain-level power limiting.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOT |
[Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOTStatus |
[Bit 0] PROCHOT Status (R0) When set, processor core frequency is reduced below the operating system request due to assertion of external PROCHOT.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::Reserved1 |
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::Reserved2 |
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::Reserved3 |
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::Reserved4 |
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::Reserved5 |
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalLog |
[Bit 17] Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalStatus |
[Bit 1] Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::TurboTransitionAttenuationLog |
[Bit 29] Turbo Transition Attenuation Log When set, indicates that the Turbo Transition Attenuation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::TurboTransitionAttenuationStatus |
[Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency is reduced below the operating system request due to Turbo transition attenuation. This prevents performance degradation due to frequent operating ratio changes.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::Uint32 |
All bit fields as a 32-bit value
| UINT64 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::Uint64 |
All bit fields as a 64-bit value
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertLog |
[Bit 26] VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.
| UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertStatus |
[Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from the Voltage Regulator.
1.8.6 
