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MdePkg[all]
1.08
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MdePkg[all]
1.08
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MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
| #define IS_GOLDMONT_PROCESSOR | ( | DisplayFamily, | |
| DisplayModel | |||
| ) |
Is Intel Atom processors based on the Goldmont microarchitecture?
| DisplayFamily | Display Family ID |
| DisplayModel | Display Model ID |
| TRUE | Yes, it is. |
| FALSE | No, it isn't. |
| #define MSR_GOLDMONT_CORE_C3_RESIDENCY 0x000003FC |
Core. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3 Residency Counter. (R/O) Value since last reset that this core is in processor-specific C3 states. Count at the same frequency as the TSC.
| ECX | MSR_GOLDMONT_CORE_C3_RESIDENCY (0x000003FC) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 0x0000064F |
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency refers to processor core frequency).
| ECX | MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS (0x0000064F) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER. |
Example usage
| #define MSR_GOLDMONT_DRAM_ENERGY_STATUS 0x00000619 |
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
| ECX | MSR_GOLDMONT_DRAM_ENERGY_STATUS (0x00000619) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_DRAM_PERF_STATUS 0x0000061B |
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
| ECX | MSR_GOLDMONT_DRAM_PERF_STATUS (0x0000061B) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_DRAM_POWER_INFO 0x0000061C |
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
| ECX | MSR_GOLDMONT_DRAM_POWER_INFO (0x0000061C) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_DRAM_POWER_LIMIT 0x00000618 |
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
| ECX | MSR_GOLDMONT_DRAM_POWER_LIMIT (0x00000618) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_FEATURE_CONTROL 0x0000003A |
Core. Control Features in Intel 64Processor (R/W).
| ECX | MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER. |
Example usage
| #define MSR_GOLDMONT_IA32_L2_QOS_MASK_0 0x00000D10 |
Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=n.
| ECX | MSR_GOLDMONT_IA32_L2_QOS_MASK_n |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER. |
Example usage
| #define MSR_GOLDMONT_IA32_L2_QOS_MASK_1 0x00000D11 |
Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=n.
| ECX | MSR_GOLDMONT_IA32_L2_QOS_MASK_n |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER. |
Example usage
| #define MSR_GOLDMONT_IA32_L2_QOS_MASK_2 0x00000D12 |
Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=n.
| ECX | MSR_GOLDMONT_IA32_L2_QOS_MASK_n |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER. |
Example usage
| #define MSR_GOLDMONT_IA32_L2_QOS_MASK_3 0x00000D13 |
Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3.
| ECX | MSR_GOLDMONT_IA32_L2_QOS_MASK_3 |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER. |
Example usage
| #define MSR_GOLDMONT_IA32_MISC_ENABLE 0x000001A0 |
Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.
| ECX | MSR_GOLDMONT_IA32_MISC_ENABLE (0x000001A0) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER. |
Example usage
| #define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390 |
Core. See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring Version 4.".
| ECX | MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. |
Example usage
| #define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391 |
Core. See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring Version 4.".
| ECX | MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. |
Example usage
| #define MSR_GOLDMONT_IA32_PQR_ASSOC 0x00000C8F |
Core. Resource Association Register (R/W).
| ECX | MSR_GOLDMONT_IA32_PQR_ASSOC (0x00000C8F) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 0x00000680 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_0_TO_IP 0x000006C0 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP 0x0000068A |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_10_TO_IP 0x000006CA |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP 0x0000068B |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_11_TO_IP 0x000006CB |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP 0x0000068C |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_12_TO_IP 0x000006CC |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP 0x0000068D |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_13_TO_IP 0x000006CD |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP 0x0000068E |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_14_TO_IP 0x000006CE |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP 0x0000068F |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_15_TO_IP 0x000006CF |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP 0x00000690 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_16_TO_IP 0x000006D0 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP 0x00000691 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_17_TO_IP 0x000006D1 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP 0x00000692 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_18_TO_IP 0x000006D2 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP 0x00000693 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_19_TO_IP 0x000006D3 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP 0x00000681 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_1_TO_IP 0x000006C1 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP 0x00000694 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_20_TO_IP 0x000006D4 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP 0x00000695 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_21_TO_IP 0x000006D5 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP 0x00000696 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_22_TO_IP 0x000006D6 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP 0x00000697 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_23_TO_IP 0x000006D7 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP 0x00000698 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_24_TO_IP 0x000006D8 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP 0x00000699 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_25_TO_IP 0x000006D9 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP 0x0000069A |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_26_TO_IP 0x000006DA |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP 0x0000069B |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_27_TO_IP 0x000006DB |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP 0x0000069C |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_28_TO_IP 0x000006DC |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP 0x0000069D |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_29_TO_IP 0x000006DD |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP 0x00000682 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_2_TO_IP 0x000006C2 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP 0x0000069E |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_30_TO_IP 0x000006DE |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP 0x0000069F |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_31_TO_IP 0x000006DF |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP 0x00000683 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_3_TO_IP 0x000006C3 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP 0x00000684 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_4_TO_IP 0x000006C4 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP 0x00000685 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_5_TO_IP 0x000006C5 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP 0x00000686 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_6_TO_IP 0x000006C6 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP 0x00000687 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_7_TO_IP 0x000006C7 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP 0x00000688 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_8_TO_IP 0x000006C8 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP 0x00000689 |
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.6 and record format in Section 17.4.8.1.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_9_TO_IP 0x000006C9 |
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See also: - Section 17.6.
| ECX | MSR_GOLDMONT_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_LASTBRANCH_TOS 0x000001C9 |
Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP.
| ECX | MSR_GOLDMONT_LASTBRANCH_TOS (0x000001C9) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_LBR_SELECT 0x000001C8 |
Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2, "Filtering of Last Branch Records.".
| ECX | MSR_GOLDMONT_LBR_SELECT (0x000001C8) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER. |
Example usage
| #define MSR_GOLDMONT_MISC_FEATURE_CONTROL 0x000001A4 |
Miscellaneous Feature Control (R/W).
| ECX | MSR_GOLDMONT_MISC_FEATURE_CONTROL (0x000001A4) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER. |
Example usage
| #define MSR_GOLDMONT_MISC_PWR_MGMT 0x000001AA |
Package. See http://biosbits.org.
| ECX | MSR_GOLDMONT_MISC_PWR_MGMT (0x000001AA) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER. |
Example usage
| #define MSR_GOLDMONT_PEBS_ENABLE 0x000003F1 |
Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling (PEBS).".
| ECX | MSR_GOLDMONT_PEBS_ENABLE (0x000003F1) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER. |
Example usage
| #define MSR_GOLDMONT_PKG_C10_RESIDENCY 0x00000632 |
Package. Note: C-state values are processor specific C-state code names,. Package C10 Residency Counter. (R/O) Value since last reset that the entire SOC is in an S0i3 state. Count at the same frequency as the TSC.
| ECX | MSR_GOLDMONT_PKG_C10_RESIDENCY (0x00000632) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_PKG_C2_RESIDENCY 0x0000060D |
Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C2 states. Count at the same frequency as the TSC.
| ECX | MSR_GOLDMONT_PKG_C2_RESIDENCY (0x0000060D) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_PKG_C3_RESIDENCY 0x000003F8 |
Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C3 states. Count at the same frequency as the TSC.
| ECX | MSR_GOLDMONT_PKG_C3_RESIDENCY (0x000003F8) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_PKG_C6_RESIDENCY 0x000003F9 |
Package. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C6 states. Count at the same frequency as the TSC.
| ECX | MSR_GOLDMONT_PKG_C6_RESIDENCY (0x000003F9) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 0x000000E2 |
Core. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates. See http://biosbits.org.
| ECX | MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL (0x000000E2) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER. |
Example usage
| #define MSR_GOLDMONT_PKG_ENERGY_STATUS 0x00000611 |
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
| ECX | MSR_GOLDMONT_PKG_ENERGY_STATUS (0x00000611) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_PKG_PERF_STATUS 0x00000613 |
Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
| ECX | MSR_GOLDMONT_PKG_PERF_STATUS (0x00000613) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_PKG_POWER_INFO 0x00000614 |
Package. PKG RAPL Parameters (R/W).
| ECX | MSR_GOLDMONT_PKG_POWER_INFO (0x00000614) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER. |
Example usage
| #define MSR_GOLDMONT_PKG_POWER_LIMIT 0x00000610 |
Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package RAPL Domain.".
| ECX | MSR_GOLDMONT_PKG_POWER_LIMIT (0x00000610) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_PKGC3_IRTL 0x0000060A |
Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates.
| ECX | MSR_GOLDMONT_PKGC3_IRTL (0x0000060A) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER. |
Example usage
| #define MSR_GOLDMONT_PKGC_IRTL1 0x0000060B |
Package. Package C6/C7S Interrupt Response Limit 1 (R/W) This MSR defines the interrupt response time limit used by the processor to manage transition to package C6 or C7S state. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates.
| ECX | MSR_GOLDMONT_PKGC_IRTL1 (0x0000060B) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER. |
Example usage
| #define MSR_GOLDMONT_PKGC_IRTL2 0x0000060C |
Package. Package C7 Interrupt Response Limit 2 (R/W) This MSR defines the interrupt response time limit used by the processor to manage transition to package C7 state. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI CStates.
| ECX | MSR_GOLDMONT_PKGC_IRTL2 (0x0000060C) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER. |
Example usage
| #define MSR_GOLDMONT_PLATFORM_INFO 0x000000CE |
Package. See http://biosbits.org.
| ECX | MSR_GOLDMONT_PLATFORM_INFO (0x000000CE) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER. |
Example usage
| #define MSR_GOLDMONT_POWER_CTL 0x000001FC |
Core. Power Control Register. See http://biosbits.org.
| ECX | MSR_GOLDMONT_POWER_CTL (0x000001FC) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER. |
Example usage
| #define MSR_GOLDMONT_PP0_ENERGY_STATUS 0x00000639 |
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".
| ECX | MSR_GOLDMONT_PP0_ENERGY_STATUS (0x00000639) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_PP1_ENERGY_STATUS 0x00000641 |
Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains.".
| ECX | MSR_GOLDMONT_PP1_ENERGY_STATUS (0x00000641) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_RAPL_POWER_UNIT 0x00000606 |
Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, "RAPL Interfaces.".
| ECX | MSR_GOLDMONT_RAPL_POWER_UNIT (0x00000606) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER. |
Example usage
| #define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0 |
| #define MSR_GOLDMONT_SGXOWNER1 MSR_GOLDMONT_SGXOWNEREPOCH1 |
| #define MSR_GOLDMONT_SGXOWNEREPOCH0 0x00000300 |
Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package. Lower 64 bits of an 128-bit external entropy value for key derivation of an enclave.
| ECX | MSR_GOLDMONT_SGXOWNEREPOCH0 (0x00000300) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_SGXOWNEREPOCH1 0x00000301 |
Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of an 128-bit external entropy value for key derivation of an enclave.
| ECX | MSR_GOLDMONT_SGXOWNEREPOCH1 (0x00000301) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_GOLDMONT_SMM_BLOCKED 0x000004E3 |
Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical processors in the package. Available only while in SMM.
| ECX | MSR_GOLDMONT_SMM_BLOCKED (0x000004E3) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER. |
Example usage
| #define MSR_GOLDMONT_SMM_DELAYED 0x000004E2 |
Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical processors in the package. Available only while in SMM and MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
| ECX | MSR_GOLDMONT_SMM_DELAYED (0x000004E2) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER. |
Example usage
| #define MSR_GOLDMONT_SMM_FEATURE_CONTROL 0x000004E0 |
Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability Enhancement. Accessible only while in SMM.
| ECX | MSR_GOLDMONT_SMM_FEATURE_CONTROL (0x000004E0) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER. |
Example usage
| #define MSR_GOLDMONT_SMM_MCA_CAP 0x0000017D |
Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM.
| ECX | MSR_GOLDMONT_SMM_MCA_CAP (0x0000017D) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER. |
Example usage
| #define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 0x0000064C |
Package. ConfigTDP Control (R/W).
| ECX | MSR_GOLDMONT_TURBO_ACTIVATION_RATIO (0x0000064C) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER. |
Example usage
| #define MSR_GOLDMONT_TURBO_GROUP_CORECNT 0x000001AE |
Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of 0 threshold is ignored.
| ECX | MSR_GOLDMONT_TURBO_GROUP_CORECNT (0x000001AE) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER. |
Example usage
| #define MSR_GOLDMONT_TURBO_RATIO_LIMIT 0x000001AD |
Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies Maximum Ratio Limit for each Core Group. Max ratio for groups with more cores must decrease monotonically. For groups with less than 4 cores, the max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must be 22 or less. For groups with more than 5 cores, the max ratio must be 16 or less..
| ECX | MSR_GOLDMONT_TURBO_RATIO_LIMIT (0x000001AD) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER. |
Example usage
| #define MSR_IA32_RTIT_CTL 0x00000570 |
Core. Trace Control Register (R/W).
| ECX | MSR_GOLDMONT_IA32_RTIT_CTL (0x00000570) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER. |
Example usage
1.8.6 
