PciExpress21.h File Reference

Data Structures
union	PCI_REG_PCIE_CAPABILITY
union	PCI_REG_PCIE_DEVICE_CAPABILITY
union	PCI_REG_PCIE_DEVICE_CONTROL
union	PCI_REG_PCIE_DEVICE_STATUS
union	PCI_REG_PCIE_LINK_CAPABILITY
union	PCI_REG_PCIE_LINK_CONTROL
union	PCI_REG_PCIE_LINK_STATUS
union	PCI_REG_PCIE_SLOT_CAPABILITY
union	PCI_REG_PCIE_SLOT_CONTROL
union	PCI_REG_PCIE_SLOT_STATUS
union	PCI_REG_PCIE_ROOT_CONTROL
union	PCI_REG_PCIE_ROOT_CAPABILITY
union	PCI_REG_PCIE_ROOT_STATUS
union	PCI_REG_PCIE_DEVICE_CAPABILITY2
union	PCI_REG_PCIE_DEVICE_CONTROL2
union	PCI_REG_PCIE_LINK_CAPABILITY2
union	PCI_REG_PCIE_LINK_CONTROL2
union	PCI_REG_PCIE_LINK_STATUS2
struct	PCI_CAPABILITY_PCIEXP
struct	SR_IOV_CAPABILITY_REGISTER
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
union	PCI_EXPRESS_REG_UNCORRECTABLE_ERROR
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
union	PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY
union	PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
struct	PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH

Macros
#define	PCI_ECAM_ADDRESS(Bus, Device, Function, Offset)   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
#define	PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT   0
#define	PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT   1
#define	PCIE_DEVICE_PORT_TYPE_ROOT_PORT   4
#define	PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT   5
#define	PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT   6
#define	PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE   7
#define	PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE   8
#define	PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT   9
#define	PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR   10
#define	PCIE_MAX_PAYLOAD_SIZE_128B   0
#define	PCIE_MAX_PAYLOAD_SIZE_256B   1
#define	PCIE_MAX_PAYLOAD_SIZE_512B   2
#define	PCIE_MAX_PAYLOAD_SIZE_1024B   3
#define	PCIE_MAX_PAYLOAD_SIZE_2048B   4
#define	PCIE_MAX_PAYLOAD_SIZE_4096B   5
#define	PCIE_MAX_PAYLOAD_SIZE_RVSD1   6
#define	PCIE_MAX_PAYLOAD_SIZE_RVSD2   7
#define	PCIE_MAX_READ_REQ_SIZE_128B   0
#define	PCIE_MAX_READ_REQ_SIZE_256B   1
#define	PCIE_MAX_READ_REQ_SIZE_512B   2
#define	PCIE_MAX_READ_REQ_SIZE_1024B   3
#define	PCIE_MAX_READ_REQ_SIZE_2048B   4
#define	PCIE_MAX_READ_REQ_SIZE_4096B   5
#define	PCIE_MAX_READ_REQ_SIZE_RVSD1   6
#define	PCIE_MAX_READ_REQ_SIZE_RVSD2   7
#define	PCIE_LINK_ASPM_L0S   BIT0
#define	PCIE_LINK_ASPM_L1   BIT1
#define	PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED   0
#define	PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED   1
#define	PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED   2
#define	PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED   3
#define	PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED   6
#define	PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED   7
#define	PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED   14
#define	PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED   15
#define	PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE   BIT0
#define	PCIE_DEVICE_CAPABILITY_OBFF_WAKE   BIT1
#define	PCIE_COMPLETION_TIMEOUT_50US_50MS   0
#define	PCIE_COMPLETION_TIMEOUT_50US_100US   1
#define	PCIE_COMPLETION_TIMEOUT_1MS_10MS   2
#define	PCIE_COMPLETION_TIMEOUT_16MS_55MS   5
#define	PCIE_COMPLETION_TIMEOUT_65MS_210MS   6
#define	PCIE_COMPLETION_TIMEOUT_260MS_900MS   9
#define	PCIE_COMPLETION_TIMEOUT_1S_3_5S   10
#define	PCIE_COMPLETION_TIMEOUT_4S_13S   13
#define	PCIE_COMPLETION_TIMEOUT_17S_64S   14
#define	PCIE_DEVICE_CONTROL_OBFF_DISABLED   0
#define	PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A   1
#define	PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B   2
#define	PCIE_DEVICE_CONTROL_OBFF_WAKE   3
#define	EFI_PCIE_CAPABILITY_BASE_OFFSET   0x100
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY   0x10
#define	EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET   0x24
#define	EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING   0x20
#define	EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET   0x28
#define	EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING   0x20
#define	EFI_PCIE_CAPABILITY_ID_ARI   0x0E
#define	EFI_PCIE_CAPABILITY_ID_ATS   0x0F
#define	EFI_PCIE_CAPABILITY_ID_SRIOV   0x10
#define	EFI_PCIE_CAPABILITY_ID_MRIOV   0x11
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES   0x04
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL   0x08
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS   0x0A
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS   0x0C
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS   0x0E
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS   0x10
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK   0x12
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF   0x14
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE   0x16
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID   0x1A
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE   0x1C
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE   0x20
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0   0x24
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1   0x28
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2   0x2C
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3   0x30
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4   0x34
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5   0x38
#define	EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE   0x3C
#define	PCI_EXP_EXT_HDR   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID   0x0001
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2   0x2
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID   0x0002
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC   0x0009
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID   0x0003
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID   0x0005
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION)   (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID   0x0006
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID   0x0004
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID   0x000D
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED)   (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED)   (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID   0x0007
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID   0x0008
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID   0x000B
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR)   (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID   0x000A
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID   0x0012
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID   0x0015
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1   0x1
#define	GET_NUMBER_RESIZABLE_BARS(x)   (x->Capability[0].ResizableBarControl.Bits.ResizableBarNumber)
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID   0x000E
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID   0x0016
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER)   (UINT16)(((POWER->DpaCapability)&0x0000000F))
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID   0x0018
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1   0x1
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID   0x0017
#define	PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1   0x1
#define	GET_TPH_TABLE_SIZE(x)   ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)

Typedefs
typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY	PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY

Detailed Description

Support for the latest PCI standard.

Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
(C) Copyright 2016 Hewlett Packard Enterprise Development LP
SPDX-License-Identifier: BSD-2-Clause-Patent

Macro Definition Documentation

#define EFI_PCIE_CAPABILITY_BASE_OFFSET   0x100

#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING   0x20

#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET   0x24

#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING   0x20

#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET   0x28

#define EFI_PCIE_CAPABILITY_ID_ARI   0x0E

#define EFI_PCIE_CAPABILITY_ID_ATS   0x0F

#define EFI_PCIE_CAPABILITY_ID_MRIOV   0x11

#define EFI_PCIE_CAPABILITY_ID_SRIOV   0x10

#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0   0x24

#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1   0x28

#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2   0x2C

#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3   0x30

#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4   0x34

#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5   0x38

#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES   0x04

#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL   0x08

#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY   0x10

#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF   0x14

#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK   0x12

#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS   0x0C

#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS   0x10

#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS   0x0A

#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE   0x1C

#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE   0x20

#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS   0x0E

#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE   0x3C

#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID   0x1A

#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE   0x16

#define GET_NUMBER_RESIZABLE_BARS

(

x

)

(x->Capability[0].ResizableBarControl.Bits.ResizableBarNumber)

#define GET_TPH_TABLE_SIZE

(

x

)

((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)

#define PCI_ECAM_ADDRESS	(		Bus,
			Device,
			Function,
			Offset
	)		(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))

Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits of Bus, Device, Function and Register are stripped prior to the generation of the address.

Parameters

Bus	PCI Bus number. Range 0..255.
Device	PCI Device number. Range 0..31.
Function	PCI Function number. Range 0..7.
Register	PCI Register number. Range 0..4095.

Returns

The encode ECAM address.

#define PCI_EXP_EXT_HDR   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER

#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL

(

ACS_EXTENDED

)

(UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))

#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE

(

ACS_EXTENDED

)

(UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))

#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID   0x000D

#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID   0x0001

#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2   0x2

#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID   0x000E

#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX

(

POWER

)

(UINT16)(((POWER->DpaCapability)&0x0000000F))

#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID   0x0016

#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID   0x0007

#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID   0x0018

#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID   0x0006

#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT

(

LINK_DECLARATION

)

(UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)

#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID   0x0005

#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID   0x0008

#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID   0x0012

#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID   0x0004

#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID   0x000A

#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID   0x0015

#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID   0x0003

#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID   0x0017

#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE

(

VENDOR

)

(UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)

#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID   0x000B

#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1   0x1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID   0x0002

#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC   0x0009

#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1   0x1

#define PCIE_COMPLETION_TIMEOUT_16MS_55MS   5

#define PCIE_COMPLETION_TIMEOUT_17S_64S   14

#define PCIE_COMPLETION_TIMEOUT_1MS_10MS   2

#define PCIE_COMPLETION_TIMEOUT_1S_3_5S   10

#define PCIE_COMPLETION_TIMEOUT_260MS_900MS   9

#define PCIE_COMPLETION_TIMEOUT_4S_13S   13

#define PCIE_COMPLETION_TIMEOUT_50US_100US   1

#define PCIE_COMPLETION_TIMEOUT_50US_50MS   0

#define PCIE_COMPLETION_TIMEOUT_65MS_210MS   6

#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED   0

#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED   15

#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED   7

#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED   3

#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED   1

#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED   14

#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED   6

#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED   2

#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE   BIT0

#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE   BIT1

#define PCIE_DEVICE_CONTROL_OBFF_DISABLED   0

#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A   1

#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B   2

#define PCIE_DEVICE_CONTROL_OBFF_WAKE   3

#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT   6

#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT   1

#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE   8

#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT   0

#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE   7

#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR   10

#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT   9

#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT   4

#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT   5

#define PCIE_LINK_ASPM_L0S   BIT0

#define PCIE_LINK_ASPM_L1   BIT1

#define PCIE_MAX_PAYLOAD_SIZE_1024B   3

#define PCIE_MAX_PAYLOAD_SIZE_128B   0

#define PCIE_MAX_PAYLOAD_SIZE_2048B   4

#define PCIE_MAX_PAYLOAD_SIZE_256B   1

#define PCIE_MAX_PAYLOAD_SIZE_4096B   5

#define PCIE_MAX_PAYLOAD_SIZE_512B   2

#define PCIE_MAX_PAYLOAD_SIZE_RVSD1   6

#define PCIE_MAX_PAYLOAD_SIZE_RVSD2   7

#define PCIE_MAX_READ_REQ_SIZE_1024B   3

#define PCIE_MAX_READ_REQ_SIZE_128B   0

#define PCIE_MAX_READ_REQ_SIZE_2048B   4

#define PCIE_MAX_READ_REQ_SIZE_256B   1

#define PCIE_MAX_READ_REQ_SIZE_4096B   5

#define PCIE_MAX_READ_REQ_SIZE_512B   2

#define PCIE_MAX_READ_REQ_SIZE_RVSD1   6

#define PCIE_MAX_READ_REQ_SIZE_RVSD2   7

Typedef Documentation

typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY