PCI_REG_PCIE_LINK_CAPABILITY Union Reference

Data Fields
struct {
UINT32   MaxLinkSpeed: 4
UINT32   MaxLinkWidth: 6
UINT32   Aspm: 2
UINT32   L0sExitLatency: 3
UINT32   L1ExitLatency: 3
UINT32   ClockPowerManagement: 1
UINT32   SurpriseDownError: 1
UINT32   DataLinkLayerLinkActive: 1
UINT32   LinkBandwidthNotification: 1
UINT32   AspmOptionalityCompliance: 1
UINT32   Reserved: 1
UINT32   PortNumber: 8
}	Bits
UINT32	Uint32

Field Documentation

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::Aspm

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::AspmOptionalityCompliance

struct { ... } PCI_REG_PCIE_LINK_CAPABILITY::Bits

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::ClockPowerManagement

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::DataLinkLayerLinkActive

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::L0sExitLatency

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::L1ExitLatency

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::LinkBandwidthNotification

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::MaxLinkSpeed

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::MaxLinkWidth

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::PortNumber

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::Reserved

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::SurpriseDownError

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::Uint32