MSR information returned for MSR index MSR_CORE2_IA32_MISC_ENABLE
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::AdjacentCacheLinePrefetchDisable |
[Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set to 1, the processor fetches the cache line that contains data currently required by the processor. When set to 0, the processor fetches cache lines that comprise a cache line pair (128 bytes). Single processor platforms should not set this bit. Server platforms should set or clear this bit based on platform performance observed in validation and testing. BIOS may contain a setup option that controls the setting of this bit.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit |
[Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See Table 2-2.
| struct { ... } MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Bits |
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::BTS |
[Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::DCUPrefetcherDisable |
[Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU L1 data cache prefetcher is disabled. The default value after reset is 0. BIOS may write '1' to disable this feature. The DCU prefetcher is an L1 data cache prefetcher. When the DCU prefetcher detects multiple loads from the same line done within a time limit, the DCU prefetcher assumes the next line will be required. The next line is prefetched in to the L1 data cache from memory or L2.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::EIST |
[Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::EISTLock |
[Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock (R/WO) When set, this bit causes the following bits to become read-only: - Enhanced Intel SpeedStep Technology Select Lock (this bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must be set before an Enhanced Intel SpeedStep Technology transition is requested. This bit is cleared on reset.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::FastStrings |
[Bit 0] Fast-Strings Enable See Table 2-2.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::FERR |
[Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the processor to indicate a pending break event within the processor 0 = Indicates compatible FERR# signaling behavior This bit must be set to 1 to support XAPIC interrupt model usage.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::HardwarePrefetcherDisable |
[Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the hardware prefetcher operation on streams of data. When clear (default), enables the prefetch queue. Disabling of the hardware prefetcher may impact processor performance.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::IDADisable |
[Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor's support of IDA is enabled. Note: the power-on default value is used by BIOS to detect hardware support of IDA. If power-on default value is 1, IDA is available in the processor. If power-on default value is 0, IDA is not available.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::IPPrefetcherDisable |
[Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP prefetcher is disabled. The default value after reset is 0. BIOS may write '1' to disable this feature. The IP prefetcher is an L1 data cache prefetcher. The IP prefetcher looks for sequential load history to determine whether to prefetch the next expected data into the L1 cache from memory or L2.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval |
[Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::MONITOR |
[Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::PEBS |
[Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See Table 2-2.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring |
[Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Reserved1 |
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Reserved10 |
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Reserved2 |
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Reserved3 |
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Reserved4 |
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Reserved5 |
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Reserved6 |
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Reserved7 |
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Reserved8 |
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Reserved9 |
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::TM2 |
[Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the thermal sensor indicates that the die temperature is at the pre-determined threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce the bus to core ratio and voltage according to the value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the processor does not change the VID signals or the bus to core ratio when the processor enters a thermally managed state. The BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is not set, this feature is not supported and BIOS must not alter the contents of the TM2 bit location. The processor is operating out of specification if both this bit and the TM1 bit are set to 0.
| UINT64 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Uint64 |
All bit fields as a 64-bit value
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::XD |
[Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
| UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable |
[Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
1.8.6 
