CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS Union Reference

Data Fields
struct {
UINT16   CacheEnable: 1
UINT16   IoEnable: 1
UINT16   MemEnable: 1
UINT16   CxlSyncBypassEnable: 1
UINT16   DriftBufferEnable: 1
UINT16   Reserved: 3
UINT16   CxlCorrectableProtocolIdFramingError: 1
UINT16   CxlUncorrectableProtocolIdFramingError: 1
UINT16   CxlUnexpectedProtocolIdDropped: 1
UINT16   Reserved2: 5
}	Bits
UINT16	Uint16

Field Documentation

struct { ... } CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS::Bits

UINT16 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS::CacheEnable

UINT16 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS::CxlCorrectableProtocolIdFramingError

UINT16 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS::CxlSyncBypassEnable

UINT16 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS::CxlUncorrectableProtocolIdFramingError

UINT16 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS::CxlUnexpectedProtocolIdDropped

UINT16 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS::DriftBufferEnable

UINT16 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS::IoEnable

UINT16 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS::MemEnable

UINT16 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS::Reserved

UINT16 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS::Reserved2

UINT16 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS::Uint16