CPUID_CACHE_PARAMS_EAX Union Reference

Data Fields
struct {
UINT32   CacheType:5
UINT32   CacheLevel:3
UINT32   SelfInitializingCache:1
UINT32   FullyAssociativeCache:1
UINT32   Reserved:4
UINT32   MaximumAddressableIdsForLogicalProcessors:12
UINT32   MaximumAddressableIdsForProcessorCores:6
}	Bits
UINT32	Uint32

Detailed Description

CPUID Cache Parameters Information returned in EAX for CPUID leaf CPUID_CACHE_PARAMS.

Field Documentation

struct { ... } CPUID_CACHE_PARAMS_EAX::Bits

Individual bit fields

UINT32 CPUID_CACHE_PARAMS_EAX::CacheLevel

[Bits 7:5] Cache level (Starts at 1).

UINT32 CPUID_CACHE_PARAMS_EAX::CacheType

[Bits 4:0] Cache type field. If CPUID_CACHE_PARAMS_CACHE_TYPE_NULL, then there is no information for the requested cache level.

UINT32 CPUID_CACHE_PARAMS_EAX::FullyAssociativeCache

[Bit 9] Fully Associative cache.

UINT32 CPUID_CACHE_PARAMS_EAX::MaximumAddressableIdsForLogicalProcessors

[Bits 25:14] Maximum number of addressable IDs for logical processors sharing this cache.

Add one to the return value to get the result. The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) is the number of unique initial APIC IDs reserved for addressing different logical processors sharing this cache.

UINT32 CPUID_CACHE_PARAMS_EAX::MaximumAddressableIdsForProcessorCores

[Bits 31:26] Maximum number of addressable IDs for processor cores in the physical package.

The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) is the number of unique Core_IDs reserved for addressing different processor cores in a physical package. Core ID is a subset of bits of the initial APIC ID. The returned value is constant for valid initial values in ECX. Valid ECX values start from 0.

UINT32 CPUID_CACHE_PARAMS_EAX::Reserved

[Bits 13:10] Reserved.

UINT32 CPUID_CACHE_PARAMS_EAX::SelfInitializingCache

[Bit 8] Self Initializing cache level (does not need SW initialization).

UINT32 CPUID_CACHE_PARAMS_EAX::Uint32

All bit fields as a 32-bit value