Xeon5600Msr.h File Reference

Data Structures
union	MSR_XEON_5600_FEATURE_CONFIG_REGISTER
union	MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER

Macros
#define	IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel)
#define	MSR_XEON_5600_FEATURE_CONFIG   0x0000013C
#define	MSR_XEON_5600_OFFCORE_RSP_1   0x000001A7
#define	MSR_XEON_5600_TURBO_RATIO_LIMIT   0x000001AD
#define	MSR_XEON_5600_IA32_ENERGY_PERF_BIAS   0x000001B0

Detailed Description

MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:

Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_XEON_5600_PROCESSOR	(		DisplayFamily,
			DisplayModel
	)

Value:

(DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x25 || \
    DisplayModel == 0x2C    \
    )                       \
   )

Is Intel(R) Xeon(R) Processor Series 5600?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

#define MSR_XEON_5600_FEATURE_CONFIG   0x0000013C

Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.

Parameters

ECX	MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.

Example usage

MSR_XEON_5600_FEATURE_CONFIG_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);

Note

MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.

#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS   0x000001B0

Package. See Table 2-2.

Parameters

ECX	MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);

Note

MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.

#define MSR_XEON_5600_OFFCORE_RSP_1   0x000001A7

Thread. Offcore Response Event Select Register (R/W).

Parameters

ECX	MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);

Note

MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.

#define MSR_XEON_5600_TURBO_RATIO_LIMIT   0x000001AD

Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1.

Parameters

ECX	MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
EAX	Lower 32-bits of MSR value. Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
EDX	Upper 32-bits of MSR value. Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.

Example usage

MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER  Msr;

Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);

Note

MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.