PentiumMsr.h File Reference

Macros
#define	IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel)
#define	MSR_PENTIUM_P5_MC_ADDR   0x00000000
#define	MSR_PENTIUM_P5_MC_TYPE   0x00000001
#define	MSR_PENTIUM_TSC   0x00000010
#define	MSR_PENTIUM_CESR   0x00000011
#define	MSR_PENTIUM_CTR0   0x00000012
#define	MSR_PENTIUM_CTR1   0x00000013

Detailed Description

MSR Definitions for Pentium Processors.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:

Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Macro Definition Documentation

#define IS_PENTIUM_PROCESSOR	(		DisplayFamily,
			DisplayModel
	)

Value:

(DisplayFamily == 0x05 && \
   (                        \
    DisplayModel == 0x01 || \
    DisplayModel == 0x02 || \
    DisplayModel == 0x04    \
    )                       \
   )

Is Pentium Processors?

Parameters

DisplayFamily	Display Family ID
DisplayModel	Display Model ID

Return values

TRUE	Yes, it is.
FALSE	No, it isn't.

#define MSR_PENTIUM_CESR   0x00000011

See Section 18.6.9.1, "Control and Event Select Register (CESR).".

Parameters

ECX	MSR_PENTIUM_CESR (0x00000011)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);

Note

MSR_PENTIUM_CESR is defined as CESR in SDM.

#define MSR_PENTIUM_CTR0   0x00000012

Section 18.6.9.3, "Events Counted.".

Parameters

ECX	MSR_PENTIUM_CTRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);

Note

MSR_PENTIUM_CTR0 is defined as CTR0 in SDM. MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.

#define MSR_PENTIUM_CTR1   0x00000013

Section 18.6.9.3, "Events Counted.".

Parameters

ECX	MSR_PENTIUM_CTRn
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);

Note

MSR_PENTIUM_CTR0 is defined as CTR0 in SDM. MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.

#define MSR_PENTIUM_P5_MC_ADDR   0x00000000

See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".

Parameters

ECX	MSR_PENTIUM_P5_MC_ADDR (0x00000000)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);

Note

MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.

#define MSR_PENTIUM_P5_MC_TYPE   0x00000001

See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".

Parameters

ECX	MSR_PENTIUM_P5_MC_TYPE (0x00000001)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);

Note

MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.

#define MSR_PENTIUM_TSC   0x00000010

See Section 17.17, "Time-Stamp Counter.".

Parameters

ECX	MSR_PENTIUM_TSC (0x00000010)
EAX	Lower 32-bits of MSR value.
EDX	Upper 32-bits of MSR value.

Example usage

UINT64  Msr;

Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);

Note

MSR_PENTIUM_TSC is defined as TSC in SDM.