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Data Structures | Macros
Cxl11.h File Reference

Data Structures

union  CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY
 
union  CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL
 
union  CXL_DVSEC_FLEX_BUS_DEVICE_STATUS
 
union  CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2
 
union  CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2
 
union  CXL_DVSEC_FLEX_BUS_DEVICE_LOCK
 
union  CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH
 
union  CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW
 
union  CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH
 
union  CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW
 
union  CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH
 
union  CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW
 
union  CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH
 
union  CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW
 
struct  CXL_1_1_DVSEC_FLEX_BUS_DEVICE
 
union  CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY
 
union  CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL
 
union  CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS
 
struct  CXL_1_1_DVSEC_FLEX_BUS_PORT
 
union  CXL_CAPABILITY_HEADER
 
union  CXL_RAS_CAPABILITY_HEADER
 
union  CXL_SECURITY_CAPABILITY_HEADER
 
union  CXL_LINK_CAPABILITY_HEADER
 
union  CXL_1_1_UNCORRECTABLE_ERROR_STATUS
 
union  CXL_1_1_UNCORRECTABLE_ERROR_MASK
 
union  CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY
 
union  CXL_CORRECTABLE_ERROR_STATUS
 
union  CXL_CORRECTABLE_ERROR_MASK
 
union  CXL_ERROR_CAPABILITIES_AND_CONTROL
 
struct  CXL_1_1_RAS_CAPABILITY_STRUCTURE
 
union  CXL_1_1_SECURITY_POLICY
 
struct  CXL_1_1_SECURITY_CAPABILITY_STRUCTURE
 
union  CXL_LINK_LAYER_CAPABILITY
 
union  CXL_LINK_LAYER_CONTROL_AND_STATUS
 
union  CXL_LINK_LAYER_RX_CREDIT_CONTROL
 
union  CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS
 
union  CXL_LINK_LAYER_TX_CREDIT_STATUS
 
union  CXL_LINK_LAYER_ACK_TIMER_CONTROL
 
union  CXL_LINK_LAYER_DEFEATURE
 
struct  CXL_1_1_LINK_CAPABILITY_STRUCTURE
 
union  CXL_IO_ARBITRATION_CONTROL
 
union  CXL_CACHE_MEMORY_ARBITRATION_CONTROL
 
union  CXL_RCRB_BASE
 

Macros

#define INTEL_CXL_DVSEC_VENDOR_ID   0x8086
 
#define CXL_DEV_DEV   0
 
#define CXL_DEV_FUNC   0
 
#define CXL_11_SIZE_ASSERT(TypeName, ExpectedSize)
 
#define CXL_11_OFFSET_ASSERT(TypeName, FieldName, ExpectedOffset)
 
#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET   0x010
 
#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET   0x014
 
#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET   0x100
 

Functions

 CXL_11_SIZE_ASSERT (CXL_RCRB_BASE, 0x8)
 
#define FLEX_BUS_DEVICE_DVSEC_ID   0
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header, 0x00)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader1, 0x04)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader2, 0x08)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability, 0x0A)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl, 0x0C)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus, 0x0E)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2, 0x10)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2, 0x12)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock, 0x14)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh, 0x18)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow, 0x1C)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh, 0x20)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow, 0x24)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh, 0x28)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow, 0x2C)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh, 0x30)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow, 0x34)
 
 CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, 0x38)
 
#define FLEX_BUS_PORT_DVSEC_ID   7
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header, 0x00)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader1, 0x04)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader2, 0x08)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability, 0x0A)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl, 0x0C)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus, 0x0E)
 
 CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, 0x10)
 
#define CXL_CAPABILITY_HEADER_OFFSET   0
 
#define CXL_RAS_CAPABILITY_HEADER_OFFSET   4
 
#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET   8
 
#define CXL_LINK_CAPABILITY_HEADER_OFFSET   0xC
 
#define CXL_IO_ARBITRATION_CONTROL_OFFSET   0x180
 
#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET   0x1C0
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus, 0x00)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask, 0x04)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity, 0x08)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus, 0x0C)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask, 0x10)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, ErrorCapabilitiesAndControl, 0x14)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog, 0x18)
 
 CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, 0x58)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, SecurityPolicy, 0x0)
 
 CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, 0x4)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability, 0x00)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus, 0x08)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl, 0x10)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditReturnStatus, 0x18)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus, 0x20)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl, 0x28)
 
 CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature, 0x30)
 
 CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, 0x38)
 
 CXL_11_SIZE_ASSERT (CXL_IO_ARBITRATION_CONTROL, 0x4)
 
 CXL_11_SIZE_ASSERT (CXL_CACHE_MEMORY_ARBITRATION_CONTROL, 0x4)
 

Detailed Description

CXL 1.1 Register definitions

This file contains the register definitions based on the Compute Express Link (CXL) Specification Revision 1.1.

Copyright (c) 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Macro Definition Documentation

#define CXL_11_OFFSET_ASSERT (   TypeName,
  FieldName,
  ExpectedOffset 
)
Value:
STATIC_ASSERT ( \
OFFSET_OF (TypeName, FieldName) == ExpectedOffset, \
"Offset of " #TypeName "." #FieldName \
" does not meet CXL 1.1 Specification requirements." \
)
STATIC_ASSERT
#define STATIC_ASSERT(Expression, Message)
Definition: Base.h:801
OFFSET_OF
#define OFFSET_OF(TYPE, Field)
Definition: Base.h:789

Macro used to verify the offset of a field in a data type at compile time and trigger a STATIC_ASSERT() with an error message if the offset of the field in the data type does not match the expected offset.

Parameters
TypeNameType name of data type to verify.
FieldNameField name in the data type specified by TypeName to verify.
ExpectedOffsetThe expected offset, in bytes, of the field specified by TypeName and FieldName.
#define CXL_11_SIZE_ASSERT (   TypeName,
  ExpectedSize 
)
Value:
STATIC_ASSERT ( \
sizeof (TypeName) == ExpectedSize, \
"Size of " #TypeName \
" does not meet CXL 1.1 Specification requirements." \
)
STATIC_ASSERT
#define STATIC_ASSERT(Expression, Message)
Definition: Base.h:801

Macro used to verify the size of a data type at compile time and trigger a STATIC_ASSERT() with an error message if the size of the data type does not match the expected size.

Parameters
TypeNameType name of data type to verify.
ExpectedSizeThe expected size, in bytes, of the data type specified by TypeName.
#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET   0x1C0

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

#define CXL_CAPABILITY_HEADER_OFFSET   0

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

#define CXL_DEV_DEV   0
#define CXL_DEV_FUNC   0
#define CXL_IO_ARBITRATION_CONTROL_OFFSET   0x180

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

#define CXL_LINK_CAPABILITY_HEADER_OFFSET   0xC

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET   0x100
#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET   0x014
#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET   0x010
#define CXL_RAS_CAPABILITY_HEADER_OFFSET   4

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET   8

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

#define FLEX_BUS_DEVICE_DVSEC_ID   0
#define FLEX_BUS_PORT_DVSEC_ID   7
#define INTEL_CXL_DVSEC_VENDOR_ID   0x8086

Function Documentation

CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
Header  ,
0x00   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DesignatedVendorSpecificHeader1  ,
0x04   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DesignatedVendorSpecificHeader2  ,
0x08   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceCapability  ,
0x0A   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceControl  ,
0x0C   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceStatus  ,
0x0E   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceControl2  ,
0x10   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceStatus2  ,
0x12   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceLock  ,
0x14   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceRange1SizeHigh  ,
0x18   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceRange1SizeLow  ,
0x1C   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceRange1BaseHigh  ,
0x20   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceRange1BaseLow  ,
0x24   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceRange2SizeHigh  ,
0x28   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceRange2SizeLow  ,
0x2C   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceRange2BaseHigh  ,
0x30   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
DeviceRange2BaseLow  ,
0x34   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_PORT  ,
Header  ,
0x00   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_PORT  ,
DesignatedVendorSpecificHeader1  ,
0x04   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_PORT  ,
DesignatedVendorSpecificHeader2  ,
0x08   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_PORT  ,
PortCapability  ,
0x0A   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_PORT  ,
PortControl  ,
0x0C   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_PORT  ,
PortStatus  ,
0x0E   
)
CXL_11_OFFSET_ASSERT ( CXL_1_1_RAS_CAPABILITY_STRUCTURE  ,
UncorrectableErrorStatus  ,
0x00   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_RAS_CAPABILITY_STRUCTURE  ,
UncorrectableErrorMask  ,
0x04   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_RAS_CAPABILITY_STRUCTURE  ,
UncorrectableErrorSeverity  ,
0x08   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_RAS_CAPABILITY_STRUCTURE  ,
CorrectableErrorStatus  ,
0x0C   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_RAS_CAPABILITY_STRUCTURE  ,
CorrectableErrorMask  ,
0x10   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_RAS_CAPABILITY_STRUCTURE  ,
ErrorCapabilitiesAndControl  ,
0x14   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_RAS_CAPABILITY_STRUCTURE  ,
HeaderLog  ,
0x18   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_SECURITY_CAPABILITY_STRUCTURE  ,
SecurityPolicy  ,
0x0   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_LINK_CAPABILITY_STRUCTURE  ,
LinkLayerCapability  ,
0x00   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_LINK_CAPABILITY_STRUCTURE  ,
LinkLayerControlStatus  ,
0x08   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_LINK_CAPABILITY_STRUCTURE  ,
LinkLayerRxCreditControl  ,
0x10   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_LINK_CAPABILITY_STRUCTURE  ,
LinkLayerRxCreditReturnStatus  ,
0x18   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_LINK_CAPABILITY_STRUCTURE  ,
LinkLayerTxCreditStatus  ,
0x20   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_LINK_CAPABILITY_STRUCTURE  ,
LinkLayerAckTimerControl  ,
0x28   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_OFFSET_ASSERT ( CXL_1_1_LINK_CAPABILITY_STRUCTURE  ,
LinkLayerDefeature  ,
0x30   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_SIZE_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_DEVICE  ,
0x38   
)
CXL_11_SIZE_ASSERT ( CXL_1_1_DVSEC_FLEX_BUS_PORT  ,
0x10   
)
CXL_11_SIZE_ASSERT ( CXL_1_1_RAS_CAPABILITY_STRUCTURE  ,
0x58   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_SIZE_ASSERT ( CXL_1_1_SECURITY_CAPABILITY_STRUCTURE  ,
0x4   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_SIZE_ASSERT ( CXL_1_1_LINK_CAPABILITY_STRUCTURE  ,
0x38   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_SIZE_ASSERT ( CXL_IO_ARBITRATION_CONTROL  ,
0x4   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_SIZE_ASSERT ( CXL_CACHE_MEMORY_ARBITRATION_CONTROL  ,
0x4   
)

CXL 1.1 Upstream and Downstream Port Subsystem Component registers The CXL.Cache and CXL.Memory Architectural register definitions Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1

CXL_11_SIZE_ASSERT ( CXL_RCRB_BASE  ,
0x8   
)